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Mon, 07 Oct 2024 01:43:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGyKfvlsryUKGk9NK4feyxacGLusdnwePQlGid8riSoUlH1xEiKnyAyOZeGAsIAjORynsbZEA== X-Received: by 2002:a05:6402:2350:b0:5c8:8c16:3971 with SMTP id 4fb4d7f45d1cf-5c8c0a8250amr17884534a12.16.1728290624922; Mon, 07 Oct 2024 01:43:44 -0700 (PDT) Received: from avogadro.local ([151.95.43.71]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c8e05bc56asm2918527a12.45.2024.10.07.01.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 01:43:44 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, qemu-stable@nongnu.org, alex.bennee@linaro.org Subject: [PATCH v2 0/2] meson: ensure we enable CMPXCHG128 on x86_64 Date: Mon, 7 Oct 2024 10:43:40 +0200 Message-ID: <20241007084342.1264048-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.46.1 MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.151, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Alex discovered that CMPXCHG128 was not enabled when building for x86_64, resulting in slow execution for wide atomic instructions, creating a huge contention when combined with a high number of cpus (found while booting android aarch64 guest on x86_64 host). The problem is that even though we enable -mcx16 option for x86_64, this is not used when testing for CMPXCHG128. Thus, we silently turn it off. x86_64 is the only architecture adding machine flags for now, so the problem is limited to this host architecture. However, the problem is generic, so define a new variable for all the -m options, so that they can be used for other such tests in the future. Based-on: <20241004223715.1275428-1-pierrick.bouvier@linaro.org> Supersedes: <20241004220123.978938-1-pierrick.bouvier@linaro.org> Paolo Bonzini (2): meson: define qemu_isa_flags meson: ensure -mcx16 is passed when detecting ATOMIC128 meson.build | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) Reviewed-By: Michael Tokarev Reviewed-by: Alex Bennée Tested-by: Alex Bennée