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[213.113.114.209]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53992ca4683sm964813e87.124.2024.10.01.15.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2024 15:14:07 -0700 (PDT) From: Strahinja Jankovic X-Google-Original-From: Strahinja Jankovic To: Beniamino Galvani , Peter Maydell , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Strahinja Jankovic Subject: [PATCH v2 0/2] Allwinner A10 SPI controller emulation Date: Wed, 2 Oct 2024 00:13:47 +0200 Message-Id: <20241001221349.8319-1-strahinja.p.jankovic@gmail.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=strahinjapjankovic@gmail.com; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch set introduces the SPI controller emulation for Allwinner A10 SoC and Cubieboard. Only master-mode functionality of the SPI controller is implemented. Since U-Boot and Linux SPI drivers for Allwinner A10 perform only byte-wide CPU access to the transmit and receive registers of the controller, the emulated controller does not implement DMA handling, and supports only byte-wide access to transmit and receive registers (half-word and word access will be treated as byte access). * diff from v1: - split patch into two parts, one implementing the peripheral and another for integrating peripheral into Allwinner A10 description - fixed issue with CS level handling when channel is not selected (idle mode); this was discovered when CS level handling was converted to a separate function - updated read and write register handling to log error when byte and half-word access not aligned to 4-byte boundary is performed - updated SPDX license tags for both header and c files - various minor fixes suggested in review Strahinja Jankovic (2): hw/ssi: Allwinner A10 SPI emulation {hw/arm,docs/system/arm}: Add SPI to Allwinner A10 docs/system/arm/cubieboard.rst | 1 + hw/arm/Kconfig | 1 + hw/arm/allwinner-a10.c | 8 + hw/ssi/Kconfig | 4 + hw/ssi/allwinner-a10-spi.c | 561 +++++++++++++++++++++++++++++ hw/ssi/meson.build | 1 + hw/ssi/trace-events | 10 + include/hw/arm/allwinner-a10.h | 2 + include/hw/ssi/allwinner-a10-spi.h | 57 +++ 9 files changed, 645 insertions(+) create mode 100644 hw/ssi/allwinner-a10-spi.c create mode 100644 include/hw/ssi/allwinner-a10-spi.h