From patchwork Mon Sep 23 03:56:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Huber X-Patchwork-Id: 1988389 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4XBq2T2dR7z1xsN for ; Mon, 23 Sep 2024 13:57:37 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ssaBq-0006Sf-DG; Sun, 22 Sep 2024 23:56:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ssaBp-0006Oe-40; Sun, 22 Sep 2024 23:56:45 -0400 Received: from dedi548.your-server.de ([85.10.215.148]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ssaBm-00013F-3y; Sun, 22 Sep 2024 23:56:44 -0400 Received: from sslproxy04.your-server.de ([78.46.152.42]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1ssaBh-0004WM-0i; Mon, 23 Sep 2024 05:56:37 +0200 Received: from [82.100.198.138] (helo=mail.embedded-brains.de) by sslproxy04.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1ssaBh-0002vO-1t; Mon, 23 Sep 2024 05:56:36 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 677744801AF; Mon, 23 Sep 2024 05:56:36 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10032) with ESMTP id ipd4KPDT_QJi; Mon, 23 Sep 2024 05:56:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id A269D4801BB; Mon, 23 Sep 2024 05:56:35 +0200 (CEST) X-Virus-Scanned: amavis at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavis, port 10026) with ESMTP id OnhaEP9SxUgN; Mon, 23 Sep 2024 05:56:35 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [192.168.96.242]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 77F6748006F; Mon, 23 Sep 2024 05:56:35 +0200 (CEST) From: Sebastian Huber To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 0/2] Fix secondary CPU reset for Xilinx Zynq 7000 Date: Mon, 23 Sep 2024 05:56:30 +0200 Message-Id: <20240923035632.81304-1-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Authenticated-Sender: smtp-embedded@poldi-networks.de X-Virus-Scanned: Clear (ClamAV 1.0.5/27406/Sun Sep 22 10:30:52 2024) Received-SPF: pass client-ip=85.10.215.148; envelope-from=sebastian.huber@embedded-brains.de; helo=dedi548.your-server.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I recently added the support for CPU1 to the xilinx-zynq-a9 machine (hw/arm/xilinx_zynq.c). However, the reset behaviour doesn't match exactly with the hardware. After a system reset (SRST), the CPU1 should execute a wfe instruction and then load the start address from 0xfffffff0: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Starting-Code-on-CPU-1 Sebastian Huber (2): hw/arm/boot: Use hooks if PSCI is disabled hw/arm/xilinx_zynq: Add CPU1 reset hw/arm/boot.c | 30 +++++++++++++++++++----------- hw/arm/xilinx_zynq.c | 25 +++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 11 deletions(-)