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[v4,00/16] riscv support for control flow integrity extensions

Message ID 20240816010711.3055425-1-debug@rivosinc.com
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Series riscv support for control flow integrity extensions | expand

Message

Deepak Gupta Aug. 16, 2024, 1:06 a.m. UTC 
v4 for riscv zicfilp and zicfiss extensions support in qemu.


Links for previous versions
[1] - v1 https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html
[2] - v2 https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa95880375a@linaro.org/T/
[3] - v3 https://lists.nongnu.org/archive/html/qemu-devel/2024-08/msg01005.html

---
v4:
   - elp state in cpu is true/false instead of enum and elp cleared
     unconditionally on trap entry. elp in *status cleared unconditionally on
     trap return. 
   - Moved logic for branch tracking in instruction translation from tb_start.
   - fixed zicfiss dependency on 'A'
   - `cpu_get_fcfien/bcfien` helpers checks fixed to check for extension first.
   - removed trace hook enums. Instead added dedicated trace helpers wherever needed.
   - fixed/simplified instruction format in decoder for lpad, sspush, sspopchk
   - simplified tlb index logic for shadow stack instructions. Removed SUM TB_FLAG
   - access to ssp CSR is gated on `cpu_get_bcfien` instead of duplicated logic
   - removed vDSO related changes for now. 
v3:
   - Removed prctl specific patches because they need to be upstream
     in kernel first.
   - As suggested by Richard, added TB flag if fcfi enabled
   - Re-worked translation for landing pad and shadow stack instructions
     to not require helper.
   - tcg helpers only for cfi violation cases so that trace hooks can be
     placed.
   - Style changes.
   - fixes assert condition in accel/tcg

v2:
   - added missed file (in v1) for shadow stack instructions implementation.

Deepak Gupta (16):
  target/riscv: Add zicfilp extension
  target/riscv: Introduce elp state and enabling controls for zicfilp
  target/riscv: save and restore elp state on priv transitions
  target/riscv: additional code information for sw check
  target/riscv: tracking indirect branches (fcfi) for zicfilp
  target/riscv: zicfilp `lpad` impl and branch tracking
  disas/riscv: enabled `lpad` disassembly
  target/riscv: Add zicfiss extension
  target/riscv: introduce ssp and enabling controls for zicfiss
  target/riscv: tb flag for shadow stack  instructions
  target/riscv: mmu changes for zicfiss shadow stack protection
  target/riscv: implement zicfiss instructions
  target/riscv: compressed encodings for sspush and sspopchk
  disas/riscv: enable disassembly for zicfiss instructions
  disas/riscv: enable disassembly for compressed sspush/sspopchk
  target/riscv: add trace-hooks for each case of sw-check exception

 disas/riscv.c                                 |  77 ++++++++-
 disas/riscv.h                                 |   4 +
 include/tcg/tcg.h                             |   1 +
 target/riscv/cpu.c                            |  17 ++
 target/riscv/cpu.h                            |  15 ++
 target/riscv/cpu_bits.h                       |  17 ++
 target/riscv/cpu_cfg.h                        |   2 +
 target/riscv/cpu_helper.c                     | 150 +++++++++++++++++-
 target/riscv/cpu_user.h                       |   1 +
 target/riscv/csr.c                            |  84 ++++++++++
 target/riscv/helper.h                         |   6 +
 target/riscv/insn16.decode                    |   2 +
 target/riscv/insn32.decode                    |  26 ++-
 target/riscv/insn_trans/trans_rva.c.inc       |  43 +++++
 target/riscv/insn_trans/trans_rvi.c.inc       |  56 +++++++
 target/riscv/insn_trans/trans_rvzicfiss.c.inc | 124 +++++++++++++++
 target/riscv/internals.h                      |   3 +
 target/riscv/op_helper.c                      |  37 +++++
 target/riscv/pmp.c                            |   5 +
 target/riscv/pmp.h                            |   3 +-
 target/riscv/tcg/tcg-cpu.c                    |  24 +++
 target/riscv/trace-events                     |   6 +
 target/riscv/translate.c                      |  48 ++++++
 23 files changed, 742 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzicfiss.c.inc