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Tue, 06 Aug 2024 17:06:56 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff58f59cc2sm93381845ad.92.2024.08.06.17.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Aug 2024 17:06:56 -0700 (PDT) From: Deepak Gupta To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Deepak Gupta Subject: [PATCH v3 00/20] riscv support for control flow integrity extensions Date: Tue, 6 Aug 2024 17:06:31 -0700 Message-ID: <20240807000652.1417776-1-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=debug@rivosinc.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sending out v3 for riscv zicfilp and zicfiss extensions support in qemu. I sent out v1 [1] and v2 [2] a while ago. [1] - https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html [2] - https://lore.kernel.org/all/ed23bcbc-fdc4-4492-803c-daa95880375a@linaro.org/T/ --- v3: - Removed prctl specific patches because they need to be upstream in kernel first. - As suggested by Richard, added TB flag if fcfi enabled - Re-worked translation for landing pad and shadow stack instructions to not require helper. - tcg helpers only for cfi violation cases so that trace hooks can be placed. - Style changes. - fixes assert condition in accel/tcg v2: - added missed file (in v1) for shadow stack instructions implementation. Deepak Gupta (20): accel/tcg: restrict assert on icount_enabled to qemu-system target/riscv: Add zicfilp extension target/riscv: Introduce elp state and enabling controls for zicfilp target/riscv: save and restore elp state on priv transitions target/riscv: additional code information for sw check target/riscv: tracking indirect branches (fcfi) for zicfilp target/riscv: zicfilp `lpad` impl and branch tracking disas/riscv: enabled `lpad` disassembly target/riscv: Add zicfiss extension target/riscv: introduce ssp and enabling controls for zicfiss target/riscv: tb flag for shadow stack instructions target/riscv: implement zicfiss instructions target/riscv: compressed encodings for sspush and sspopchk target/riscv: mmu changes for zicfiss shadow stack protection target/riscv: shadow stack mmu index for shadow stack instructions disas/riscv: enable disassembly for zicfiss instructions disas/riscv: enable disassembly for compressed sspush/sspopchk target/riscv: add trace-hooks for each case of sw-check exception linux-user: permit RISC-V CFI dynamic entry in VDSO linux-user: Add RISC-V zicfilp support in VDSO accel/tcg/cpu-exec.c | 2 +- disas/riscv.c | 71 +++++++- disas/riscv.h | 4 + linux-user/gen-vdso-elfn.c.inc | 7 + linux-user/riscv/vdso-64.so | Bin 3944 -> 4128 bytes linux-user/riscv/vdso.S | 50 ++++++ target/riscv/cpu.c | 17 ++ target/riscv/cpu.h | 28 +++ target/riscv/cpu_bits.h | 29 +++ target/riscv/cpu_cfg.h | 2 + target/riscv/cpu_helper.c | 167 +++++++++++++++++- target/riscv/cpu_user.h | 1 + target/riscv/csr.c | 106 +++++++++++ target/riscv/helper.h | 3 + target/riscv/insn16.decode | 4 + target/riscv/insn32.decode | 23 ++- target/riscv/insn_trans/trans_rva.c.inc | 55 ++++++ target/riscv/insn_trans/trans_rvi.c.inc | 68 +++++++ target/riscv/insn_trans/trans_rvzicfiss.c.inc | 155 ++++++++++++++++ target/riscv/internals.h | 4 + target/riscv/op_helper.c | 49 +++++ target/riscv/pmp.c | 5 + target/riscv/pmp.h | 3 +- target/riscv/tcg/tcg-cpu.c | 20 +++ target/riscv/trace-events | 6 + target/riscv/translate.c | 75 ++++++++ 26 files changed, 945 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzicfiss.c.inc