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Fri, 02 Aug 2024 01:34:33 -0700 (PDT) From: Ajeet Singh X-Google-Original-From: Ajeet Singh To: qemu-devel@nongnu.org Cc: Warner Losh , Ajeet Singh Subject: [PATCH 00/18] bsd-user: Comprehensive RISCV support Date: Fri, 2 Aug 2024 18:34:05 +1000 Message-Id: <20240802083423.142365-1-itachis@FreeBSD.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2f; envelope-from=itachis6234@gmail.com; helo=mail-io1-xd2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch series provides support for the RISC-V 64-bit architecture, enabling signal processing, system call handling, threading, and memory management tailored to RISC-V. Mark Corbin (16): bsd-user: Implement RISC-V CPU initialization and main loop bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Implement RISC-V TLS register setup bsd-user: Add prototype for RISC-V TLS register setup bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Define RISC-V register structures and register copying bsd-user: Add RISC-V signal trampoline setup function bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Add RISC-V thread setup and initialization support bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Define RISC-V system call structures and constants bsd-user: Define RISC-V signal handling structures and constants bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Warner Losh (2): bsd-user: Add generic RISC-V64 target definitions bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++ bsd-user/riscv/target.h | 20 +++ bsd-user/riscv/target_arch.h | 27 ++++ bsd-user/riscv/target_arch_cpu.c | 29 +++++ bsd-user/riscv/target_arch_cpu.h | 147 ++++++++++++++++++++++ bsd-user/riscv/target_arch_elf.h | 48 ++++++++ bsd-user/riscv/target_arch_reg.h | 88 +++++++++++++ bsd-user/riscv/target_arch_signal.h | 75 ++++++++++++ bsd-user/riscv/target_arch_sigtramp.h | 46 +++++++ bsd-user/riscv/target_arch_sysarch.h | 41 +++++++ bsd-user/riscv/target_arch_thread.h | 47 +++++++ bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++ bsd-user/riscv/target_syscall.h | 38 ++++++ configs/targets/riscv64-bsd-user.mak | 4 + 14 files changed, 833 insertions(+) create mode 100644 bsd-user/riscv/signal.c create mode 100644 bsd-user/riscv/target.h create mode 100644 bsd-user/riscv/target_arch.h create mode 100644 bsd-user/riscv/target_arch_cpu.c create mode 100644 bsd-user/riscv/target_arch_cpu.h create mode 100644 bsd-user/riscv/target_arch_elf.h create mode 100644 bsd-user/riscv/target_arch_reg.h create mode 100644 bsd-user/riscv/target_arch_signal.h create mode 100644 bsd-user/riscv/target_arch_sigtramp.h create mode 100644 bsd-user/riscv/target_arch_sysarch.h create mode 100644 bsd-user/riscv/target_arch_thread.h create mode 100644 bsd-user/riscv/target_arch_vmparam.h create mode 100644 bsd-user/riscv/target_syscall.h create mode 100644 configs/targets/riscv64-bsd-user.mak