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[for-9.2,v6,00/12] riscv: QEMU RISC-V IOMMU Support

Message ID 20240801154334.1009852-1-dbarboza@ventanamicro.com
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Series riscv: QEMU RISC-V IOMMU Support | expand

Message

Daniel Henrique Barboza Aug. 1, 2024, 3:43 p.m. UTC 
Hi,

In this new version the most notable change is how we're dealing with
ICVEC updates. Instead of hardcoding the vectors being used in
riscv-iommu-pci, a new interface was created to allow IOMMU devices to
receive ICVEC updates and act accordingly.

riscv-iommu-pci will receive this notification, mark any existing MSIX
vectors as 'unused' and use the new ones provided by ICVEC.

Series based on master. 

Patches missing acks/reviews: 3, 12

Changes from v5:
- patch 11: dropped
- patch 2:
  - align RISCV_IOMMU_REG_SIZE
- patch 3:
  - RISCV_IOMMU_REG_IVEC renamed to RISCV_IOMMU_REG_ICVEC to match the
    reg name used in the specification
  - created riscv_iommu_process_icvec_update() to process updates done
    in ICVEC (via riscv_iommu_mmio_write())
  - created a new 'icvec_update' interface to allow devices to receive
    new ICVEC vectors
  - added riscv_iommu_mrif_notification trace at the end of
    riscv_iommu_msi_write()
- patch 5:
  - added a new icvec_vectors[] RISCVIOMMUStatePci property
  - created a new riscv_iommu_pci_icvec_update() function that
    implements the new 'icvec_update' IOMMU interface. This function
    will update all MSIX vector usage based on the current CIV, FIV,
    PMIV and PIV values
- patch 12 (former 13):
  - added more details on what to expect when adding a riscv-iommu-pci
    device in the 'virt' machine
- v5 link: https://lore.kernel.org/qemu-riscv/20240708173501.426225-1-dbarboza@ventanamicro.com/


Daniel Henrique Barboza (4):
  pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
  test/qtest: add riscv-iommu-pci tests
  qtest/riscv-iommu-test: add init queues test
  docs/specs: add riscv-iommu

Tomasz Jeznach (8):
  exec/memtxattr: add process identifier to the transaction attributes
  hw/riscv: add riscv-iommu-bits.h
  hw/riscv: add RISC-V IOMMU base emulation
  hw/riscv: add riscv-iommu-pci reference device
  hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
  hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
  hw/riscv/riscv-iommu: add ATS support
  hw/riscv/riscv-iommu: add DBG support

 docs/specs/index.rst             |    1 +
 docs/specs/pci-ids.rst           |    2 +
 docs/specs/riscv-iommu.rst       |   80 +
 docs/system/riscv/virt.rst       |   13 +
 hw/riscv/Kconfig                 |    4 +
 hw/riscv/meson.build             |    1 +
 hw/riscv/riscv-iommu-bits.h      |  417 ++++++
 hw/riscv/riscv-iommu-pci.c       |  208 +++
 hw/riscv/riscv-iommu.c           | 2392 ++++++++++++++++++++++++++++++
 hw/riscv/riscv-iommu.h           |  152 ++
 hw/riscv/trace-events            |   15 +
 hw/riscv/trace.h                 |    1 +
 hw/riscv/virt.c                  |   33 +-
 include/exec/memattrs.h          |    5 +
 include/hw/pci/pci.h             |    1 +
 include/hw/riscv/iommu.h         |   36 +
 meson.build                      |    1 +
 tests/qtest/libqos/meson.build   |    4 +
 tests/qtest/libqos/riscv-iommu.c |   76 +
 tests/qtest/libqos/riscv-iommu.h |  100 ++
 tests/qtest/meson.build          |    1 +
 tests/qtest/riscv-iommu-test.c   |  234 +++
 22 files changed, 3776 insertions(+), 1 deletion(-)
 create mode 100644 docs/specs/riscv-iommu.rst
 create mode 100644 hw/riscv/riscv-iommu-bits.h
 create mode 100644 hw/riscv/riscv-iommu-pci.c
 create mode 100644 hw/riscv/riscv-iommu.c
 create mode 100644 hw/riscv/riscv-iommu.h
 create mode 100644 hw/riscv/trace-events
 create mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/riscv/iommu.h
 create mode 100644 tests/qtest/libqos/riscv-iommu.c
 create mode 100644 tests/qtest/libqos/riscv-iommu.h
 create mode 100644 tests/qtest/riscv-iommu-test.c