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Tsirkin" , BALATON Zoltan Subject: [PATCH-for-9.1 v3 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Date: Thu, 1 Aug 2024 17:00:19 +0200 Message-ID: <20240801150021.52977-1-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org v3: Move comment from patch 2 to 1 v2: Move reset values from Realize to ResetHold (mst) Philippe Mathieu-Daudé (2): hw/pci-host/gt64120: Reset config registers during RESET phase hw/pci-host/gt64120: Set PCI base address register write mask hw/pci-host/gt64120.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-)