[PATCH-for-9.1,v2,0/2] hw/pci-host/gt64120: Set PCI base address register write mask

Message ID	20240801145630.52680-1-philmd@linaro.org
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, "Michael S . Tsirkin" <mst@redhat.com> Subject: [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Date: Thu, 1 Aug 2024 16:56:28 +0200 Message-ID: <20240801145630.52680-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	hw/pci-host/gt64120: Set PCI base address register write mask \| expand [PATCH-for-9.1,v2,0/2] hw/pci-host/gt64120: Set PCI base address register write mask [PATCH-for-9.1,v2,1/2] hw/pci-host/gt64120: Reset config registers during RESET phase [PATCH-for-9.1,v2,2/2] hw/pci-host/gt64120: Set PCI base address register write mask

Message ID

20240801145630.52680-1-philmd@linaro.org

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From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
 Aurelien Jarno <aurelien@aurel32.net>, "Michael S . Tsirkin" <mst@redhat.com>
Subject: [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address
 register write mask
Date: Thu,  1 Aug 2024 16:56:28 +0200
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Series

hw/pci-host/gt64120: Set PCI base address register write mask | expand

Message

Philippe Mathieu-Daudé Aug. 1, 2024, 2:56 p.m. UTC

v2: Move reset values from Realize to ResetHold (mst)

Philippe Mathieu-Daudé (2):
  hw/pci-host/gt64120: Reset config registers during RESET phase
  hw/pci-host/gt64120: Set PCI base address register write mask

 hw/pci-host/gt64120.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)