mbox series

[v2,00/24] riscv support for control flow integrity extensions

Message ID 20240729175327.73705-1-debug@rivosinc.com
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Series riscv support for control flow integrity extensions | expand

Message

Deepak Gupta July 29, 2024, 5:53 p.m. UTC 
Sending out v2 for riscv zicfilp and zicfiss extensions support in qemu.
I sent out v1 [1] last week and had missed adding `trans_zicfiss.c.inc` in
commit titled "implement zicifss instructions" and commit titled "shadow
stack mmu index for shadow stack instructions". Revising both those commits
and sending out patch series again.

[1] - https://lists.nongnu.org/archive/html/qemu-devel/2024-07/msg06017.html

---
v2:
- added missed file (in v1) for shadow stack instructions implementation.

Deepak Gupta (24):
  target/riscv: Add zicfilp extension
  target/riscv: Introduce elp state and enabling controls for zicfilp
  target/riscv: save and restore elp state on priv transitions
  target/riscv: additional code information for sw check
  target/riscv: tracking indirect branches (fcfi) for zicfilp
  target/riscv: zicfilp `lpad` impl and branch tracking
  disas/riscv: enabled `lpad` disassembly
  linux-user/syscall: introduce prctl for indirect branch tracking
  linux-user/riscv: implement indirect branch tracking prctls
  target/riscv: Add zicfiss extension
  target/riscv: introduce ssp and enabling controls for zicfiss
  target/riscv: tb flag for shadow stack  instructions
  target/riscv: implement zicfiss instructions
  target/riscv: compressed encodings for sspush and sspopchk
  target/riscv: mmu changes for zicfiss shadow stack protection
  target/riscv: shadow stack mmu index for shadow stack instructions
  linux-user/syscall: introduce prctl for shadow stack enable/disable
  linux-user/riscv: setup/teardown zicfiss shadow stack for qemu-user
  disas/riscv: enable disassembly for zicfiss instructions
  disas/riscv: enable disassembly for compressed sspush/sspopchk
  target/riscv: add trace-hooks for each case of sw-check exception
  linux-user: permit RISC-V CFI dynamic entry in VDSO
  linux-user: Add RISC-V zicfilp support in VDSO
  linux-user/riscv: Adding zicfiss/lp extension in hwprobe syscall

 disas/riscv.c                                 |  71 +++++++-
 disas/riscv.h                                 |   4 +
 linux-user/gen-vdso-elfn.c.inc                |   7 +
 linux-user/riscv/cpu_loop.c                   |  50 ++++++
 linux-user/riscv/target_cpu.h                 |   7 +
 linux-user/riscv/target_prctl.h               |  70 ++++++++
 linux-user/riscv/vdso-64.so                   | Bin 3944 -> 4128 bytes
 linux-user/riscv/vdso.S                       |  50 ++++++
 linux-user/syscall.c                          |  40 +++++
 target/riscv/cpu.c                            |  21 +++
 target/riscv/cpu.h                            |  28 +++
 target/riscv/cpu_bits.h                       |  23 +++
 target/riscv/cpu_cfg.h                        |   2 +
 target/riscv/cpu_helper.c                     | 166 +++++++++++++++++-
 target/riscv/cpu_user.h                       |   1 +
 target/riscv/csr.c                            | 106 +++++++++++
 target/riscv/helper.h                         |   6 +
 target/riscv/insn16.decode                    |   4 +
 target/riscv/insn32.decode                    |  23 ++-
 target/riscv/insn_trans/trans_rva.c.inc       |  55 ++++++
 target/riscv/insn_trans/trans_rvi.c.inc       |  52 ++++++
 target/riscv/insn_trans/trans_rvzicfiss.c.inc | 155 ++++++++++++++++
 target/riscv/internals.h                      |   4 +
 target/riscv/op_helper.c                      |  63 +++++++
 target/riscv/pmp.c                            |   5 +
 target/riscv/pmp.h                            |   3 +-
 target/riscv/tcg/tcg-cpu.c                    |  20 +++
 target/riscv/trace-events                     |   6 +
 target/riscv/translate.c                      |  80 +++++++++
 29 files changed, 1114 insertions(+), 8 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvzicfiss.c.inc