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Thu, 11 Jul 2024 07:18:59 -0700 (PDT) Received: from wheely.local0.net ([203.220.44.216]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70b54ec730fsm3308904b3a.173.2024.07.11.07.18.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jul 2024 07:18:58 -0700 (PDT) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?b?RnLDqWTDqXJp?= =?utf-8?b?YyBCYXJyYXQ=?= , Harsh Prateek Bora , qemu-devel@nongnu.org Subject: [PATCH 00/18] ppc/pnv: Better big-core model, lpar-per-core, PC unit Date: Fri, 12 Jul 2024 00:18:32 +1000 Message-ID: <20240711141851.406677-1-npiggin@gmail.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Primary motivation for this series is to improve big-core support. This also fixes POWER8 SMT running Linux with the msgsnd fix and setting lpar-per-core mode (which is always true on POWER8). I think I accounted for all feedback from Cedric and Harsh from the last RFC (except a couple of style suggestions from Harsh). Since rfc: - Fixed POWER8 SMT so it doesn't have to be disabled. - Fixed inadvertent spapr SMT bug. - Renamed PnvCPUState.core pointer to pnv_core. (Harsh) - Moved where it is initialised (clg) - Avoided most qdev_get_machine() calls by adding a PnvMachineState pointer from PnvChip, new patch 3 (clg). - Rename TB state to use camel case (Harsh and clg) - Add comment to explain SPRC/SPRD is only accessed with powernv. - Use mc->desc for error messages and avoid splitting machine init handlers (Harsh). - Add max_smt_threads class attribute to avoid duplicating checks (clg) - Rename processor_id() class method to get_pir_tir (Harsh and clg) - Add a comment for get_pir_tir() (clg) - Allow get_pir_tir() to be passed NULL pointers to avoid dummy pir/tir variables (Harsh) - Move the PPC_CPU_HAS_CORE_SIBLINGS macros to inline functions (clg) - Invert them (test for single-thread rather than for siblings) because the callers read a little better that way (Harsh). - Propagate lpar and big-core options down to chip and core levels rather than having to test machine (clg) - Significantly split the big-core patch (clg). - Rework big-core device-tree handling to simplify it (clg). - Make new has_smt_siblings property bool (Harsh) - Make the big-core timebase tod quirk a machine class property rather than machine state (Harsh). Thanks, Nick Nicholas Piggin (18): target/ppc: Fix msgsnd for POWER8 ppc/pnv: Add pointer from PnvCPUState to PnvCore ppc/pnv: Add a pointer from PnvChip to PnvMachineState ppc/pnv: Move timebase state into PnvCore target/ppc: Move SPR indirect registers into PnvCore ppc/pnv: specialise init for powernv8/9/10 machines ppc/pnv: Extend chip_pir class method to TIR as well ppc: Add a core_index to CPUPPCState for SMT vCPUs target/ppc: Add helpers to check for SMT sibling threads ppc: Add has_smt_siblings property to CPUPPCState ppc/pnv: Add a big-core mode that joins two regular cores ppc/pnv: Add allow for big-core differences in DT generation ppc/pnv: Implement big-core PVR for Power9/10 ppc/pnv: Implement Power9 CPU core thread state indirect register ppc/pnv: Add POWER10 ChipTOD quirk for big-core ppc/pnv: Add big-core machine property ppc/pnv: Implement POWER10 PC xscom registers for direct controls ppc/pnv: Add an LPAR per core machine option include/hw/core/cpu.h | 8 + include/hw/ppc/pnv.h | 7 + include/hw/ppc/pnv_chip.h | 6 +- include/hw/ppc/pnv_core.h | 31 ++++ target/ppc/cpu.h | 41 ++--- hw/ppc/pnv.c | 298 ++++++++++++++++++++++++++++------- hw/ppc/pnv_chiptod.c | 7 +- hw/ppc/pnv_core.c | 130 +++++++++++++-- hw/ppc/spapr_cpu_core.c | 16 +- system/cpus.c | 10 ++ target/ppc/cpu_init.c | 26 +-- target/ppc/excp_helper.c | 69 ++++---- target/ppc/misc_helper.c | 104 ++++++------ target/ppc/timebase_helper.c | 82 +++++----- 14 files changed, 601 insertions(+), 234 deletions(-) Tested-by: Cédric Le Goater