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[RFC,v3,0/2] Support RISC-V CSR read/write in Qtest environment

Message ID 20240625153555.104088-1-ivan.klokov@syntacore.com
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Series Support RISC-V CSR read/write in Qtest environment | expand

Message

Ivan Klokov June 25, 2024, 3:35 p.m. UTC 
These patches add functionality for unit testing RISC-V-specific registers.
The first patch adds a Qtest backend, and the second implements a simple test.

---
v3:
   - Refactor, delete additions to libqos framework
---

Ivan Klokov (2):
  target/riscv: Add RISC-V CSR qtest support
  tests/qtest: QTest example for RISC-V CSR register

 target/riscv/cpu.c           | 14 ++++++
 target/riscv/cpu.h           |  3 ++
 target/riscv/csr.c           | 53 +++++++++++++++++++++-
 tests/qtest/libqtest.c       | 27 ++++++++++++
 tests/qtest/libqtest.h       | 14 ++++++
 tests/qtest/meson.build      |  2 +
 tests/qtest/riscv-csr-test.c | 85 ++++++++++++++++++++++++++++++++++++
 7 files changed, 197 insertions(+), 1 deletion(-)
 create mode 100644 tests/qtest/riscv-csr-test.c