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envelope-from=hchauhan@ventanamicro.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org All the CPUs may or may not implement the debug triggers. Some CPUs may implement only debug specification v0.13 and not sdtrig ISA extension. This patchset, adds sdtrig ISA as an extension which can be turned on or off by sdtrig= option. It is turned off by default. When debug is true and sdtrig is false, the behaviour is as defined in debug specification v0.13. If sdtrig is turned on, the behaviour is as defined in the sdtrig ISA extension. The "sdtrig" string is concatenated to ISA string when debug or sdtrig is enabled. Changes from v1: - Replaced the debug property with ext_sdtrig - Marked it experimenatal by naming it x-sdtrig - x-sdtrig is added to ISA string - Reversed the patch order Changes from v2: - Mark debug property as deprecated and replace internally with sdtrig extension - setting/unsetting debug property shows warning and sets/unsets ext_sdtrig - sdtrig is added to ISA string as RISC-V debug specification is frozen Changes from v3: - debug propery is not deprecated but it is superceded by sdtrig extension - Mcontrol6 support is not published when only debug property is turned on as debug spec v0.13 doesn't define mcontrol6 match triggers. - Enabling sdtrig extension turns of debug property and a warning is printed. This doesn't break debug specification implemenation since sdtrig is backward compatible with debug specification. - Disable debug property and enable sdtrig by default for Ventana's Veyron CPUs. Himanshu Chauhan (3): target/riscv: Enable mcontrol6 triggers only when sdtrig is selected target/riscv: Expose sdtrig ISA extension target/riscv: Enable sdtrig for Ventana's Veyron CPUs target/riscv/cpu.c | 14 ++++++- target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 2 +- target/riscv/debug.c | 92 +++++++++++++++++++++++++----------------- target/riscv/machine.c | 2 +- 5 files changed, 70 insertions(+), 41 deletions(-)