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[98.147.55.211]) by smtp.gmail.com with ESMTPSA id v8-20020a17090a458800b0029af67d4fd0sm4034901pjg.44.2024.03.01.21.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Mar 2024 21:16:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 00/41] target/sparc: Implement VIS4 Date: Fri, 1 Mar 2024 19:15:20 -1000 Message-Id: <20240302051601.53649-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I whipped this up over the Christmas break, but I'm just now getting around to posting. I have not attempted to model the newer cpus that have these features, but it is possible to enable the features manually via -cpu properties. Possibly the first 6 or 7 patches should be taken sooner than later because they fix bugs in existing VIS[12] code. I remove cpu_fpr[], so that we can use gvec on the same memory. r~ Richard Henderson (41): linux-user/sparc: Add more hwcap bits for sparc64 target/sparc: Fix FEXPAND target/sparc: Fix FMUL8x16 target/sparc: Fix FMUL8x16A{U,L} target/sparc: Fix FMULD8*X16 target/sparc: Fix FPMERGE target/sparc: Split out do_ms16b target/sparc: Perform DFPREG/QFPREG in decodetree target/sparc: Remove gen_dest_fpr_D target/sparc: Remove cpu_fpr[] target/sparc: Use gvec for VIS1 parallel add/sub target/sparc: Implement FMAf extension target/sparc: Add feature bits for VIS 3 target/sparc: Implement ADDXC, ADDXCcc target/sparc: Implement CMASK instructions target/sparc: Implement FCHKSM16 target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD target/sparc: Implement FNMUL target/sparc: Implement FLCMP target/sparc: Implement FMEAN16 target/sparc: Implement FPADD64 FPSUB64 target/sparc: Implement FPADDS, FPSUBS target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 target/sparc: Implement FSLL, FSRL, FSRA, FSLAS target/sparc: Implement LDXEFSR target/sparc: Implement LZCNT target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd target/sparc: Implement PDISTN target/sparc: Implement UMULXHI target/sparc: Implement XMULX target/sparc: Enable VIS3 feature bit target/sparc: Implement IMA extension target/sparc: Add feature bit for VIS4 target/sparc: Implement FALIGNDATAi target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS target/sparc: Implement VIS4 comparisons target/sparc: Implement FPMIN, FPMAX target/sparc: Implement SUBXC, SUBXCcc target/sparc: Implement MWAIT target/sparc: Implement monitor asis target/sparc: Enable VIS4 feature bit target/sparc/asi.h | 4 + target/sparc/helper.h | 36 +- linux-user/elfload.c | 51 +- target/sparc/cpu.c | 12 + target/sparc/fop_helper.c | 104 ++++ target/sparc/ldst_helper.c | 4 + target/sparc/translate.c | 960 +++++++++++++++++++++++++++++---- target/sparc/vis_helper.c | 526 +++++++++++------- target/sparc/cpu-feature.h.inc | 4 + target/sparc/insns.decode | 338 +++++++++--- 10 files changed, 1626 insertions(+), 413 deletions(-)