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Tue, 20 Feb 2024 13:11:25 -0800 (PST) Date: Tue, 20 Feb 2024 21:11:20 +0000 Mime-Version: 1.0 X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240220211123.2664977-1-komlodi@google.com> Subject: [PATCH v4 0/3] hw/i2c: smbus: Reset fixes From: Joe Komlodi To: qemu-devel@nongnu.org Cc: komlodi@google.com, venture@google.com, minyard@acm.org, peter.maydell@linaro.org Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3fRXVZQcKCjIYcaZcRWUccUZS.QcaeSai-RSjSZbcbUbi.cfU@flex--komlodi.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Changelog: v3 -> v4 Patch 1 - Removed the rest of the I3CBus class definition that I forgot to remove in v3 v2 -> v3 Patch 1 - Removed I3CBus class definition, since it was unneeded. - whitespace fixes - Changed enter_reset to hold_reset Patch 2 - Moved pointer returned by object_get_canonical_path outside of printf so it can be freed Patch 3 - Changed enter_reset to hold_reset v1 -> v2 - Dropped 4th patch "hw/i2c: smbus: mux: Reset SMBusDevice state on reset". After more testing and Corey's comment, I realized it wasn't needed. Original message: Hi all, This series adds some resets for SMBus and for the I2C core. Along with it, we make SMBus slave error printing a little more helpful. These reset issues were very infrequent, they would maybe occur in 1 out of hundreds of resets in our testing, but the way they happen is pretty straightforward. Basically as long as a reset happens in the middle of a transaction, the state of the old transaction would still partially be there after the reset. Once a new transaction comes in, the partial stale state can cause the new transaction to incorrectly fail. Thanks, Joe Joe Komlodi (3): hw/i2c: core: Add reset hw/i2c/smbus_slave: Add object path on error prints hw/i2c: smbus_slave: Reset state on reset hw/i2c/core.c | 19 +++++++++++++++++++ hw/i2c/smbus_slave.c | 17 +++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-)