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[123.243.155.241]) by smtp.gmail.com with ESMTPSA id pl6-20020a17090b268600b00297138f0496sm6232621pjb.31.2024.02.19.20.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 20:19:31 -0800 (PST) From: Nicholas Piggin To: qemu-ppc@nongnu.org Cc: Nicholas Piggin , qemu-devel@nongnu.org, Richard Henderson Subject: [RFC PATCH 0/3] real ll/sc emulation Date: Tue, 20 Feb 2024 14:19:19 +1000 Message-ID: <20240220041922.373029-1-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=npiggin@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org I've been toying with how we might do a more faithful ll/sc emulation. Our cmpxchg based one actually had problems on some firmware code we're testing. The using the dirty memory bitmap to detect stores coming from other CPUs and invalidating active protection / reservations seems to be a possibility. This passes some basic atomic and locking stress tests with mttcg, and boots Linux. Excuse some of the hacky / ugly / unfinished bits of code, I missed getting into details of vfio, migration, and making it clean. Just wanted to hear thoughts on the general idea at the moment. The code doesn't seem to be _terribly_ tricky, but there are some tricks around the store-conditional side of it where we have to take a mutex, do the tlb lookup with possible recursion into the code protected by that mutex, verify the protection is still active, and then modify memory. There is only a single lock now, but if that beomes a problem we *might* be able to split it via physical address hash. But that doesn't help uncontended performance or contention on the same address, which are probably the two most important cases. (I will submit the TCG TLB coherency fix patch separately, difficulty at the moment is creating a test case for it that does not require subsequent patches!) Thanks, Nick Nicholas Piggin (3): accel/tcg: Fix TCG TLB coherency race with physical dirty bit clearing tcg: add a ll/sc protection facility target/ppc: Implement reservation protection for larx/stcx include/exec/cputlb.h | 7 ++ include/exec/exec-all.h | 1 - include/exec/ram_addr.h | 42 ++++++- include/exec/ramlist.h | 10 ++ include/hw/core/cpu.h | 5 + target/ppc/cpu-param.h | 4 + target/ppc/helper.h | 2 + accel/stubs/tcg-stub.c | 4 - accel/tcg/cputlb.c | 235 ++++++++++++++++++++++++++++++++++++--- hw/core/cpu-common.c | 5 + hw/vfio/common.c | 2 +- hw/virtio/vhost.c | 1 + system/memory.c | 3 + system/physmem.c | 7 ++ target/ppc/cpu_init.c | 4 + target/ppc/mem_helper.c | 132 ++++++++++++++++++++++ target/ppc/translate.c | 128 +++++---------------- system/memory_ldst.c.inc | 3 +- 18 files changed, 467 insertions(+), 128 deletions(-)