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[v2,0/3] riscv: set vstart_eq_zero on mark_vs_dirty

Message ID 20240216135719.1034289-1-dbarboza@ventanamicro.com
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Series riscv: set vstart_eq_zero on mark_vs_dirty | expand

Message

Daniel Henrique Barboza Feb. 16, 2024, 1:57 p.m. UTC 
Hi,

This second version is based on feedback gave on the Gitlab bug [1] by
Vladimir Isaev. For this approach to work the 'vstart_eq_zero' flag
must be updated regardless of 'mstatus_vs' being marked as DIRTY or
not - there's no guarantee that we'll clean mstatus_vs after each change
in 'vstart'.

Patches based on alistair/riscv-to-apply.next.


[1] https://gitlab.com/qemu-project/qemu/-/issues/1976

Changes from v1:
- patch 3:
  - always update vstart_eq_zero, not only if "mstatus_vs !=
    EXT_STATUS_DIRTY"
- v1 link: https://lore.kernel.org/qemu-riscv/20240216112806.997948-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (3):
  trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too
  trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
  target/riscv/translate.c: set vstart_eq_zero in mark_vs_dirty()

 target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++------------------
 target/riscv/translate.c                | 20 ++++++++++++++++++
 2 files changed, 27 insertions(+), 21 deletions(-)