[0/2] ARM Sbsa-ref: Enable CPU cluster topology

Enable CPU cluster support on SbsaQemu platform, so that users can
specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this
topology can be passed to the firmware through DT cpu-map.

xiongyining1480 (2):
  hw/arm/sbsa-ref:Enable CPU cluster on ARM sbsa machine
  hw/arm/sbsa-ref: Add cpu-map to device tree

 hw/arm/sbsa-ref.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

W dniu 27.12.2023 o 13:07, Xiong Yining pisze:
> Enable CPU cluster support on SbsaQemu platform, so that users can
> specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this
> topology can be passed to the firmware through DT cpu-map.
> 
> xiongyining1480 (2):
>    hw/arm/sbsa-ref:Enable CPU cluster on ARM sbsa machine
>    hw/arm/sbsa-ref: Add cpu-map to device tree
> 
>   hw/arm/sbsa-ref.c | 36 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
> 

Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

Booted system with "-smp 8,sockets=2,clusters=2,cores=1,threads=2" and 
got what I wanted:

         cpus {
                 #size-cells = <0x00>;
                 #address-cells = <0x02>;

                 cpu-map {
                         socket0 {
                                 cluster0 {
                                         core0 {
                                                 thread0 {
                                                         cpu = <0x8007>;
                                                 };
                                                 thread1 {
                                                         cpu = <0x8006>;
                                                 };
                                         };
                                 };
                                 cluster1 {
                                         core0 {
                                                 thread0 {
                                                         cpu = <0x8005>;
                                                 };
                                                 thread1 {
                                                         cpu = <0x8004>;
                                                 };
                                         };
                                 };
                         };
                         socket1 {
                                 cluster0 {
                                         core0 {
                                                 thread0 {
                                                         cpu = <0x8003>;
                                                 };
                                                 thread1 {
                                                         cpu = <0x8002>;
                                                 };
                                         };
                                 };
                                 cluster1 {
                                         core0 {
                                                 thread0 {
                                                         cpu = <0x8001>;
                                                 };
                                                 thread1 {
                                                         cpu = <0x8000>;
                                                 };
                                         };
                                 };
                         };
                 };

                 cpu@0 {
                         phandle = <0x8007>;
                         reg = <0x00 0x00>;
                 };

                 cpu@1 {
                         phandle = <0x8006>;
                         reg = <0x00 0x01>;
                 };

                 cpu@2 {
                         phandle = <0x8005>;
                         reg = <0x00 0x02>;
                 };

                 cpu@3 {
                         phandle = <0x8004>;
                         reg = <0x00 0x03>;
                 };

                 cpu@4 {
                         phandle = <0x8003>;
                         reg = <0x00 0x04>;
                 };

                 cpu@5 {
                         phandle = <0x8002>;
                         reg = <0x00 0x05>;
                 };

                 cpu@6 {
                         phandle = <0x8001>;
                         reg = <0x00 0x06>;
                 };

                 cpu@7 {
                         phandle = <0x8000>;
                         reg = <0x00 0x07>;
                 };
         };