From patchwork Sat Dec 16 18:27:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Tardieu X-Patchwork-Id: 1876974 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ssvjz2RHNz23p3 for ; Sun, 17 Dec 2023 05:28:55 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rEZOH-0000TK-Jv; Sat, 16 Dec 2023 13:27:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rEZOF-0000Qh-TE; Sat, 16 Dec 2023 13:27:55 -0500 Received: from zoidberg.rfc1149.net ([195.154.227.159]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rEZOC-0006Wn-OM; Sat, 16 Dec 2023 13:27:55 -0500 Received: from buffy.. (buffy [192.168.147.6]) by zoidberg.rfc1149.net (Postfix) with ESMTP id CBEC980025; Sat, 16 Dec 2023 19:27:46 +0100 (CET) Authentication-Results: zoidberg.rfc1149.net; dmarc=fail (p=none dis=none) header.from=rfc1149.net Authentication-Results: zoidberg.rfc1149.net; spf=fail smtp.mailfrom=rfc1149.net From: Samuel Tardieu To: qemu-devel@nongnu.org Cc: Anton Kochkov , qemu-arm@nongnu.org, Alexandre Iooss , Alistair Francis , Peter Maydell , Samuel Tardieu Subject: [PATCH 0/3] Add "num-prio-bits" property for Cortex-M devices Date: Sat, 16 Dec 2023 19:27:37 +0100 Message-ID: <20231216182740.3305724-1-sam@rfc1149.net> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Received-SPF: pass client-ip=195.154.227.159; envelope-from=sam@rfc1149.net; helo=zoidberg.rfc1149.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch series builds on a discussion initiated by Anton Kochkov on this list in 2022. It allows setting the appropriate number of priority bits for Cortex-M devices. For example, FreeRTOS checks at startup that the right number of priority bits is available in order to guarantee its runtime structures safety. They added a configuration option specially for QEMU to disable this check because QEMU always use 2 bits for Cortex-M0/M0+/M1 and 8 bits for other devices. While this change allows the number of priority bits to be properly configured, it keeps the same default as before in order to preserve backward compatibility. Based-on: <20220813112559.1974427-1-anton.kochkov@proton.me> ([PATCH] hw/arm/nvic: implement "num-prio-bits" property) Samuel Tardieu (3): hw/intc/armv7m_nvic: add "num-prio-bits" property hw/arm/armv7m: alias the NVIC "num-prio-bits" property hw/arm/socs: configure priority bits for existing SOCs hw/arm/armv7m.c | 2 ++ hw/arm/stellaris.c | 2 ++ hw/arm/stm32f100_soc.c | 1 + hw/arm/stm32f205_soc.c | 1 + hw/arm/stm32f405_soc.c | 1 + hw/intc/armv7m_nvic.c | 23 ++++++++++++++++++++++- 6 files changed, 29 insertions(+), 1 deletion(-)