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Tue, 12 Dec 2023 21:19:43 -0800 (PST) Received: from localhost ([157.82.205.15]) by smtp.gmail.com with UTF8SMTPSA id b8-20020a170903228800b001d052d1aaf2sm9446438plh.101.2023.12.12.21.19.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 12 Dec 2023 21:19:43 -0800 (PST) From: Akihiko Odaki Subject: [PATCH v7 0/4] gdbstub and TCG plugin improvements Date: Wed, 13 Dec 2023 14:19:28 +0900 Message-Id: <20231213-riscv-v7-0-a760156a337f@daynix.com> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAOA+eWUC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyzHUUlJIzE vPSU3UzU4B8JSMDI2NDI0Nj3aLM4uQy3bTkZEszEwNLC7PkNCWg2oKi1LTMCrA50bG1tQAquOi hVwAAAA== To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Fabiano Rosas Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.4 Received-SPF: none client-ip=2607:f8b0:4864:20::1136; envelope-from=akihiko.odaki@daynix.com; helo=mail-yw1-x1136.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This series extracts fixes and refactorings that can be applied independently from "[PATCH v9 00/23] plugins: Allow to read registers". The patch "target/riscv: Move MISA limits to class" was replaced with patch "target/riscv: Move misa_mxl_max to class" since I found instances may have different misa_ext_mask. V6 -> V7: Rebased. V5 -> V6: Added patch "default-configs: Add TARGET_XML_FILES definition". Rebased. V4 -> V5: Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max". V3 -> V4: Added patch "gdbstub: Check if gdb_regs is NULL". V2 -> V3: Restored patch sets from the previous version. Rebased to commit 800485762e6564e04e2ab315132d477069562d91. V1 -> V2: Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64". Added patch "target/riscv: Initialize gdb_core_xml_file only once". Dropped patch "target/riscv: Remove misa_mxl validation". Dropped patch "target/riscv: Move misa_mxl_max to class". Dropped patch "target/riscv: Validate misa_mxl_max only once". Signed-off-by: Akihiko Odaki --- Akihiko Odaki (4): hw/riscv: Use misa_mxl instead of misa_mxl_max target/riscv: Remove misa_mxl validation target/riscv: Move misa_mxl_max to class target/riscv: Validate misa_mxl_max only once target/riscv/cpu.h | 4 +- hw/riscv/boot.c | 2 +- target/riscv/cpu.c | 139 ++++++++++++++++++++++++++------------------- target/riscv/gdbstub.c | 12 ++-- target/riscv/kvm/kvm-cpu.c | 10 ++-- target/riscv/machine.c | 7 +-- target/riscv/tcg/tcg-cpu.c | 44 ++------------ target/riscv/translate.c | 3 +- 8 files changed, 109 insertions(+), 112 deletions(-) --- base-commit: 9c74490bff6c8886a922008d0c9ce6cae70dd17e change-id: 20231213-riscv-fcc9640986cf Best regards,