Message ID | 20231030151528.1138131-1-hans-erik.floryd@rt-labs.com |
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[213.136.33.86]) by smtp.gmail.com with ESMTPSA id j18-20020a2e3c12000000b002b95eb96ab7sm1282274lja.18.2023.10.30.08.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 08:15:35 -0700 (PDT) From: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> To: alistair@alistair23.me, peter.maydell@linaro.org, marcandre.lureau@redhat.com, pbonzini@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org, philmd@linaro.org Cc: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Subject: [PATCH v3 0/3] stm32f2xx_usart: implement TX interrupts Date: Mon, 30 Oct 2023 16:15:15 +0100 Message-ID: <20231030151528.1138131-1-hans-erik.floryd@rt-labs.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=hans-erik.floryd@rt-labs.com; helo=mail-lj1-x235.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org |
Series | stm32f2xx_usart: implement TX interrupts | expand |
On Mon, 30 Oct 2023 at 15:15, Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> wrote: > > Generate interrupt if either of the TXE, TC or RXNE bits are active > and the corresponding interrupt enable bit is set. > > v3: > - Drop patch "hw/char/stm32f2xx_usart: Update IRQ when SR is read" as > it is not required Applied to target-arm.next. Thanks for this contribution! -- PMM