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Sat, 28 Oct 2023 11:30:31 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 24A3D20040; Sat, 28 Oct 2023 11:30:31 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9C22B2004F; Sat, 28 Oct 2023 11:30:29 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 28 Oct 2023 11:30:29 +0000 (GMT) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v3 0/3] pnv nest1 chiplet model Date: Sat, 28 Oct 2023 06:30:23 -0500 Message-Id: <20231028113026.23510-1-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 2cK0m3JP-HFzOPqLpJHPUXlN8uqH2pT_ X-Proofpoint-ORIG-GUID: bQ9AqDuq-tIdozIQuMFpMivRHST1eKpy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-28_09,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=489 priorityscore=1501 impostorscore=0 mlxscore=0 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 clxscore=1011 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310280088 Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hello, For modularity reasons the P10 processor chip is split into multiple chiplets individually controlled and managed by the pervasive logic. The boundaries of these chiplets are defined based on physical design parameters like clock grids, the nature of the functional units as well as their pervasive requirements (e.g. clock domains). Examples of chiplet in the P10 chip are processor cores and caches, memory controllers or IO interfaces like PCIe. Partitioning the processor chip into these chiplets allows the pervasive logic to test, initialize, control and manage these chip partitions individually. In this series, we create a nest1 chiplet model and implements the chiplet control scom registers on nest1 chiplet. The chiplet control registers does the initialization and configuration of a chiplet. In this PATCH Cedric's review comments has been addressed to add a new QOM model for pervasive chiplet and initialize and realize in nest1 chiplet model. /nest1_chiplet (pnv-nest1-chiplet) /perv_chiplet (pnv-pervasive-chiplet) /xscom-chiplet-control-regs[0] (memory-region) Chalapathi V (3): hw/ppc: Add pnv pervasive common chiplet units hw/ppc: Add nest1 chiplet model hw/ppc: Nest1 chiplet wiring hw/ppc/meson.build | 2 + hw/ppc/pnv.c | 11 ++ hw/ppc/pnv_nest1_chiplet.c | 104 +++++++++++++ hw/ppc/pnv_pervasive.c | 237 ++++++++++++++++++++++++++++++ include/hw/ppc/pnv_chip.h | 2 + include/hw/ppc/pnv_nest_chiplet.h | 39 +++++ include/hw/ppc/pnv_pervasive.h | 47 ++++++ include/hw/ppc/pnv_xscom.h | 3 + 8 files changed, 445 insertions(+) create mode 100644 hw/ppc/pnv_nest1_chiplet.c create mode 100644 hw/ppc/pnv_pervasive.c create mode 100644 include/hw/ppc/pnv_nest_chiplet.h create mode 100644 include/hw/ppc/pnv_pervasive.h