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Sat, 28 Oct 2023 01:54:34 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([191.255.2.33]) by smtp.gmail.com with ESMTPSA id t15-20020a81830f000000b00594fff48796sm1604325ywf.75.2023.10.28.01.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Oct 2023 01:54:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v6 00/12] RVA22U64 profile support Date: Sat, 28 Oct 2023 05:54:15 -0300 Message-ID: <20231028085427.707060-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1134; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x1134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Based-on: 20231023153927.435083-1-dbarboza@ventanamicro.com ("[PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support") Hi, This version has several changes proposed by Drew in v5 and a design change after a discussion we have in the v3 review [1]. Notable changes: - zicbop extension flag is added (patch 1). Given that this is an actual extension, not a 'named feature', and we already implement is as a no-op, we're adding the flag to make our riscv,isa compliant with what the profile mandates; - zic64b is no longer an user flag. zic64b is a named extension, a glorified way of telling that we're using 64 byte cache blocks. Users can indirectly set it to true/false by simply editing cbo{m,p,z}_blocksize; - zic64b, an all future named extensions, are now exposed in query-cpu-model-expansion (patch 3); - marking a profile as 'false' in the command line no longer disables its mandatory extensions in the CPU. Since profile flags are disabled by default in all current CPUs, setting 'rva22u64=false' will cause no change of state in the CPU, i.e. it'll do nothing. This is the same mechanic that RVG already uses and we'll make profiles behave the same way. We'll not "be creative" and interpret a 'false' from the command line mean something different than the existing 'false'. If we want a way to mass disable CPU extensions we can implement cleaner ways of doing it. See [1] for even more context/rant about the previous design and why we're changing it. Patches based on top of: [PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support Patches missing acks: patches 1,2,3 Changes from v5: - patch 1 (new): - add zicbop extension flag - patch 2 (patch 1 from v5): - zic64b no longer exposed as user flag, no longer throwing user warnings - patch 3 (new): - change query-cpu-model-expansion to include named extensions like zic64b - patch 4 (patch 2 from v5): - remove extra whitespace in profile description comment - added "(nor for zic64b, despite it having a cfg offset)" in the profile description comment - moved 'NULL' to its own line in riscv_profiles[] - added 'zicbop' as a mandatory profile extension - patch 6 (patch 4 from v5): - add 64 bit CPU restriction for profiles - marking a profile as 'false' no longer removes all the mandatory extensions of the CPU model, making it compatible with what RVG does: profileA=true means "enable all mandatory extensions of profileA" profileA=false means "do not enable all mandatory extensions of profileA" - v5 link: https://lore.kernel.org/qemu-riscv/20231025234459.581697-1-dbarboza@ventanamicro.com/ [1] https://lore.kernel.org/qemu-riscv/e3f53179-7f7e-42a9-8a13-a81bf1beeb89@ventanamicro.com/ Daniel Henrique Barboza (12): target/riscv: add zicbop extension flag target/riscv/tcg: add 'zic64b' support riscv-qmp-cmds.c: expose named features in cpu_model_expansion target/riscv: add rva22u64 profile definition target/riscv/kvm: add 'rva22u64' flag as unavailable target/riscv/tcg: add user flag for profile support target/riscv/tcg: add MISA user options hash target/riscv/tcg: add riscv_cpu_write_misa_bit() target/riscv/tcg: handle profile MISA bits target/riscv/tcg: add hash table insert helpers target/riscv/tcg: honor user choice for G MISA bits target/riscv/tcg: warn if profile exts are disabled hw/riscv/virt.c | 5 + target/riscv/cpu.c | 48 +++++- target/riscv/cpu.h | 15 ++ target/riscv/cpu_cfg.h | 3 + target/riscv/kvm/kvm-cpu.c | 7 +- target/riscv/riscv-qmp-cmds.c | 30 +++- target/riscv/tcg/tcg-cpu.c | 277 ++++++++++++++++++++++++++++------ 7 files changed, 335 insertions(+), 50 deletions(-)