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([191.255.2.33]) by smtp.gmail.com with ESMTPSA id jw4-20020a170903278400b001ca485b8515sm9252548plb.91.2023.10.25.06.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 06:50:09 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 0/9] RVA22U64 profile support Date: Wed, 25 Oct 2023 10:49:52 -0300 Message-ID: <20231025135001.531224-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Based-on: 20231023153927.435083-1-dbarboza@ventanamicro.com ("[PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support") Hi, This version has changes based on feedback from Drew and Zhiwei in v3. Most notable changes: - profiles flags now have the same weight as individual extension, meaning that left-to-right ordering will change the resulting configuration; - warnings are no longer being shown if the user disables a profile. We'll make a documentation note about why disabling a profile is an advanced feature instead of warning users simply because they set a single flag to 'off'; - warnings are being shown if the user disables a mandatory extension of a profile the user is enabling. This will cover the scenario where the user is disabling an extension by mistake or, if it's intentional, the user can safely ignore it; - RVG is being handled closer to a profile. This is something that we decided to do here, in patch 8, to keep consistent with what we're doing with profiles in patch 9. This means that we're now throwing warnings if the user set g=true and then disabled a G extension (IMAFD_zicsr_zifencei) in the command line. Series is based on top of: [PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support Patches missing acks: 3, 7, 8, 9 Changes from v3: - patch 1: - added RVI in the profile definition - patch 3: - removed disable profile warning from set() callback - mandatory extensions from a profile that are enabled/disabled has the same priority as individual extensions that are enabled/disabled. Left-to-right ordering matters for the final result - patch 6: - change profile misa bits priority to be the same as regular misa bits set in the command line - patch 7 (new): - add hash helpers - patch 8 (new): - honor user choice for RVG MISA bits - patch 9 (new): - throw user warnings if profile extensions are disabled in the command line - v3 link: https://lore.kernel.org/qemu-riscv/20231020223951.357513-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (9): target/riscv: add rva22u64 profile definition target/riscv/kvm: add 'rva22u64' flag as unavailable target/riscv/tcg: add user flag for profile support target/riscv/tcg: add MISA user options hash target/riscv/tcg: add riscv_cpu_write_misa_bit() target/riscv/tcg: handle profile MISA bits target/riscv/tcg: add hash table insert helpers target/riscv/tcg: honor user choice for G MISA bits target/riscv/tcg: warn if profile exts are disabled target/riscv/cpu.c | 20 +++ target/riscv/cpu.h | 12 ++ target/riscv/kvm/kvm-cpu.c | 7 +- target/riscv/tcg/tcg-cpu.c | 249 ++++++++++++++++++++++++++++++------- 4 files changed, 245 insertions(+), 43 deletions(-)