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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ji5-20020a170903324500b001b06c106844sm8578661plb.151.2023.10.25.00.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 00:27:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org Subject: [PATCH 00/29] tcg: Introduce TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 00:26:38 -0700 Message-Id: <20231025072707.833943-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Inspired by some other patch review this week, expose a pair of comparison operators that map to the "test" comparison that is available on many architectures. Convert target/alpha to use this as an exemplar. r~ Richard Henderson (29): tcg: Introduce TCG_COND_TST{EQ,NE} tcg/optimize: Split out arg_is_const_val tcg/optimize: Split out do_constant_folding_cond1 tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 tcg/optimize: Split out arg_new_constant tcg/optimize: Handle TCG_COND_TST{EQ,NE} tcg/aarch64: Support TCG_COND_TST{EQ,NE} tcg/aarch64: Generate TBZ, TBNZ tcg/arm: Support TCG_COND_TST{EQ,NE} tcg/i386: Pass x86 condition codes to tcg_out_cmov tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp tcg/i386: Add rexw argument to tcg_out_testi tcg/i386: Support TCG_COND_TST{EQ,NE} tcg/loongarch64: Support TCG_COND_TST{EQ,NE} tcg/mips: Support TCG_COND_TST{EQ,NE} tcg/riscv: Support TCG_COND_TST{EQ,NE} tcg/sparc64: Implement tcg_out_extrl_i64_i32 tcg/sparc64: Hoist read of tcg_cond_to_rcond tcg/sparc64: Pass TCGCond to tcg_out_cmp tcg/sparc64: Support TCG_COND_TST{EQ,NE} tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel tcg/ppc: Create tcg_out_and_rc tcg/ppc: Support TCG_COND_TST{EQ,NE} tcg/s390x: Support TCG_COND_TST{EQ,NE} tcg/tci: Support TCG_COND_TST{EQ,NE} target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} target/alpha: Use TCG_COND_TST{EQ,NE} for CMOVLB{C,S} target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero include/tcg/tcg-cond.h | 49 +++- tcg/aarch64/tcg-target-con-set.h | 4 +- target/alpha/translate.c | 94 +++---- tcg/optimize.c | 444 ++++++++++++++++++++++--------- tcg/tcg.c | 4 +- tcg/tci.c | 14 + docs/devel/tcg-ops.rst | 2 + tcg/aarch64/tcg-target.c.inc | 156 ++++++++--- tcg/arm/tcg-target.c.inc | 59 ++-- tcg/i386/tcg-target.c.inc | 111 ++++---- tcg/loongarch64/tcg-target.c.inc | 56 ++-- tcg/mips/tcg-target.c.inc | 41 +++ tcg/ppc/tcg-target.c.inc | 213 ++++++++------- tcg/riscv/tcg-target.c.inc | 20 +- tcg/s390x/tcg-target.c.inc | 127 ++++++--- tcg/sparc64/tcg-target.c.inc | 67 +++-- 16 files changed, 998 insertions(+), 463 deletions(-)