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([177.45.186.249]) by smtp.gmail.com with ESMTPSA id h1-20020a170902704100b001c61921d4d2sm1992373plt.302.2023.10.20.15.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 15:39:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 0/6] riscv: RVA22U64 profile support Date: Fri, 20 Oct 2023 19:39:45 -0300 Message-ID: <20231020223951.357513-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Based-on: 20231017221226.136764-1-dbarboza@ventanamicro.com ("[PATCH v2 0/6] riscv: zicntr/zihpm flags and disable support") Hi, The most notable change in this new version is that we're back to enabling/disabling profile extensions during the property set() callback, instead of doing an extra step during realize(), to give more predictability on how profiles can interact with each other. In the previous version profiles would be committed based on a fixed internal order. This time they'll be evaluated via the common left-to-right ordering we're used to in QEMU. This means that these two configurations are different: -cpu rv64,profileA=true,profileB=false "enable all mandatory extensions of profile A, then disable all mandatory extensions of profile B" -cpu rv64,profileB=false,profileA=true "disable all mandatory extensions of profile B, then enable all mandatory extensions of profile A" We're also adding an user warning if a profile is disabled. Between implementing profile disablement (disable all its mandatory extensions) versus not implementing it and having a flag that does nothing if the user set it to 'off', we're choosing the least of two ills with the former. However, given that it is a very niche feature that is hard to use it right and very easy to do something silly, an user warning is appropriate. Series is based on top of the zicntr/zihpm implementation series since they're both part of the rva22u64 profile. Patches missing acks: 3, 6 Changes from v2: - patches 1 and 2 from v2: moved to a separated series - patches 6, 9 and 10 from v2: dropped - patch 3: - use the set() callback to enable/disable mandatory profile extensions - patch 6: - handle profile MISA bits in the profile set() callback - v2 link: https://lore.kernel.org/qemu-riscv/20231006132134.1135297-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (6): target/riscv: add rva22u64 profile definition target/riscv/kvm: add 'rva22u64' flag as unavailable target/riscv/tcg: add user flag for profile support target/riscv/tcg: add MISA user options hash target/riscv/tcg: add riscv_cpu_write_misa_bit() target/riscv/tcg: handle profile MISA bits target/riscv/cpu.c | 20 +++++++ target/riscv/cpu.h | 12 ++++ target/riscv/kvm/kvm-cpu.c | 7 ++- target/riscv/tcg/tcg-cpu.c | 118 ++++++++++++++++++++++++++++++++----- 4 files changed, 142 insertions(+), 15 deletions(-)