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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id x18-20020a17090300d200b001b891259eddsm685682plc.197.2023.10.16.23.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:41:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 00/20] target/sparc: Cleanup condition codes etc Date: Mon, 16 Oct 2023 23:40:49 -0700 Message-Id: <20231017064109.681935-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This was part of my guess for some of the performance problems. I saw compute_all_sub quite high in the profile at some point, and I believe that the test case has a partially rotated loop such that "cmp" is in a delay slot, and so the gen_compare fast path for CC_OP_SUB is not visible to the conditional branch that uses the output of the compare. Which means that helper_compute_psr gets called much more often that we'd like. Move away from CC_OP to explicit computation of conditions. This is modeled on target/arm for the (mostly) separate representation of the bits. We can pack icc.[NV] and xcc.[NV] into the same target_ulong, but Z and C cannot share. After removing CC_OP, clean up the handling of conditions so that we can minimize additional setcond required for env->cond. Finally, inline some division, which can make use of the new out-of-line exception path, which means we can expand UDIVX and SDIVX with very few host insns. The 64/32 UDIV insn needs only a few more. Leave UDIVcc and SDIV* out of line, as the overflow and saturation computation in these cases is really too large to inline. r~ Based-on: 20231017061244.681584-1-richard.henderson@linaro.org ("[PATCH v2 00/90] target/sparc: Convert to decodetree") Richard Henderson (20): target/sparc: Introduce cpu_put_psr_icc target/sparc: Split psr and xcc into components target/sparc: Remove CC_OP_DIV target/sparc: Remove CC_OP_LOGIC target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV target/sparc: Remove CC_OP leftovers target/sparc: Remove DisasCompare.is_bool target/sparc: Change DisasCompare.c2 to int target/sparc: Always copy conditions into a new temporary target/sparc: Do flush_cond in advance_jump_cond target/sparc: Merge gen_branch2 into advance_pc target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond target/sparc: Use DISAS_EXIT in do_wrpsr target/sparc: Merge gen_op_next_insn into only caller target/sparc: Record entire jump condition in DisasContext target/sparc: Discard cpu_cond at the end of each insn target/sparc: Implement UDIVX and SDIVX inline target/sparc: Implement UDIV inline linux-user/sparc/target_cpu.h | 4 +- target/sparc/cpu.h | 58 +- target/sparc/helper.h | 9 +- linux-user/sparc/cpu_loop.c | 23 +- linux-user/sparc/signal.c | 2 +- target/sparc/cc_helper.c | 471 ------------- target/sparc/cpu.c | 1 - target/sparc/helper.c | 156 ++--- target/sparc/int32_helper.c | 5 - target/sparc/int64_helper.c | 5 - target/sparc/machine.c | 44 +- target/sparc/translate.c | 1225 ++++++++++++++------------------- target/sparc/win_helper.c | 55 +- target/sparc/meson.build | 1 - 14 files changed, 724 insertions(+), 1335 deletions(-) delete mode 100644 target/sparc/cc_helper.c