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Sat, 14 Oct 2023 03:01:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEJPPzLv3B2hhTU+kbdrp8cTBhg+XQsWcEuRBKrHmE3YSF576uFmn2++7wMIe9KBmgTcGh/qQ== X-Received: by 2002:a50:9f4f:0:b0:53e:3b8f:8a5a with SMTP id b73-20020a509f4f000000b0053e3b8f8a5amr3516549edf.39.1697277683161; Sat, 14 Oct 2023 03:01:23 -0700 (PDT) Received: from [192.168.10.118] ([2001:b07:6468:f312:5e2c:eb9a:a8b6:fd3e]) by smtp.gmail.com with ESMTPSA id p14-20020aa7cc8e000000b005340d9d042bsm12318850edt.40.2023.10.14.03.01.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Oct 2023 03:01:22 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 00/18] target/i386: decoder changes for 8.2 Date: Sat, 14 Oct 2023 12:01:02 +0200 Message-ID: <20231014100121.109817-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This includes: - implementing SHA and CMPccXADD instruction extensions - introducing a new mechanism for flags writeback that avoids a tricky failure - converting the more orthogonal parts of the one-byte opcode map, as well as the CMOVcc and SETcc instructions. Tested by booting several 32-bit and 64-bit guests. Paolo Paolo Bonzini (18): target/i386: group common checks in the decoding phase target/i386: validate VEX.W for AVX instructions target/i386: implement SHA instructions tests/tcg/i386: initialize more registers in test-avx tests/tcg/i386: test-avx: add test cases for SHA new instructions target/i386: accept full MemOp in gen_ext_tl target/i386: introduce flags writeback mechanism target/i386: implement CMPccXADD target/i386: do not clobber A0 in POP translation target/i386: reintroduce debugging mechanism target/i386: move 00-5F opcodes to new decoder target/i386: adjust decoding of J operand target/i386: split eflags computation out of gen_compute_eflags target/i386: move 60-BF opcodes to new decoder target/i386: move operand load and writeback out of gen_cmovcc1 target/i386: move remaining conditional operations to new decoder target/i386: remove now converted opcodes from old decoder target/i386: remove gen_op target/i386/cpu.c | 4 +- target/i386/ops_sse.h | 128 ++++ target/i386/tcg/decode-new.c.inc | 605 ++++++++++++++-- target/i386/tcg/decode-new.h | 41 +- target/i386/tcg/emit.c.inc | 726 ++++++++++++++++++- target/i386/tcg/ops_sse_header.h.inc | 14 + target/i386/tcg/translate.c | 1001 +++----------------------- tests/tcg/i386/Makefile.target | 2 +- tests/tcg/i386/test-avx.c | 8 + tests/tcg/i386/test-avx.py | 3 +- tests/tcg/i386/test-flags.c | 37 + 11 files changed, 1593 insertions(+), 976 deletions(-) create mode 100644 tests/tcg/i386/test-flags.c