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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 00/19] riscv: split TCG/KVM accelerators from cpu.c Date: Mon, 25 Sep 2023 14:56:50 -0300 Message-ID: <20230925175709.35696-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, This new version has a simple copyright change in the tcg-cpu.c file, patch 01, suggested by Alistair in v3. No other changes made. All patches acked/reviewed. Changes from v3: - patch 1: - use cpu.c copyright notice in tcg-cpu.c - v3 link: https://lore.kernel.org/qemu-riscv/20230920112020.651006-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (19): target/riscv: introduce TCG AccelCPUClass target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c target/riscv: move riscv_tcg_ops to tcg-cpu.c target/riscv/cpu.c: add .instance_post_init() target/riscv: move 'host' CPU declaration to kvm.c target/riscv/cpu.c: mark extensions arrays as 'const' target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c target/riscv: make riscv_add_satp_mode_properties() public target/riscv: remove kvm-stub.c target/riscv: introduce KVM AccelCPUClass target/riscv: move KVM only files to kvm subdir target/riscv/kvm: do not use riscv_cpu_add_misa_properties() target/riscv/cpu.c: export set_misa() target/riscv/tcg: introduce tcg_cpu_instance_init() target/riscv/cpu.c: make misa_ext_cfgs[] 'const' target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c target/riscv/cpu.c: export isa_edata_arr[] target/riscv/cpu: move priv spec functions to tcg-cpu.c hw/intc/riscv_aplic.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 988 ++------------------------ target/riscv/cpu.h | 30 +- target/riscv/csr.c | 1 + target/riscv/kvm-stub.c | 30 - target/riscv/{kvm.c => kvm/kvm-cpu.c} | 120 +++- target/riscv/{ => kvm}/kvm_riscv.h | 4 - target/riscv/kvm/meson.build | 1 + target/riscv/meson.build | 4 +- target/riscv/tcg/meson.build | 2 + target/riscv/tcg/tcg-cpu.c | 883 +++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.h | 27 + 13 files changed, 1113 insertions(+), 981 deletions(-) delete mode 100644 target/riscv/kvm-stub.c rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (91%) rename target/riscv/{ => kvm}/kvm_riscv.h (89%) create mode 100644 target/riscv/kvm/meson.build create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/tcg-cpu.c create mode 100644 target/riscv/tcg/tcg-cpu.h