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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id q3-20020a170902788300b001b531e8a000sm5707763pll.157.2023.09.16.15.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 15:01:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: git@xen0n.name, c@jia.je, gaosong@loongson.cn, yangxiaojuan@loongson.cn Subject: [PATCH 0/7] tcg/loongarch64: Improvements for 128-bit load/store Date: Sat, 16 Sep 2023 15:01:44 -0700 Message-Id: <20230916220151.526140-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For tcg generated code, use new registers with load so that we never overlap the input address, so that we can simplify address build for 64-bit user-only. For tcg out-of-line code, implement the host/ headers to for atomic 128-bit load and store, reducing the cases for which we must raise EXCP_ATOMIC. r~ Based-on: 20230916171223.521545-1-richard.henderson@linaro.org ("[PULL v2 00/39] tcg patch queue") Richard Henderson (7): tcg: Add C_N2_I1 tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h host/include/loongarch64: Add atomic16 load and store accel/tcg: Remove redundant case in store_atom_16 accel/tcg: Fix condition for store_atom_insert_al16 .../include/loongarch64/host/atomic128-ldst.h | 52 +++++++++++++++++++ host/include/loongarch64/host/cpuinfo.h | 21 ++++++++ .../loongarch64/host/load-extract-al16-al8.h | 39 ++++++++++++++ .../loongarch64/host/store-insert-al16.h | 12 +++++ tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/loongarch64/tcg-target.h | 8 +-- accel/tcg/cputlb.c | 2 +- tcg/tcg.c | 5 ++ util/cpuinfo-loongarch.c | 35 +++++++++++++ accel/tcg/ldst_atomicity.c.inc | 14 ++--- tcg/loongarch64/tcg-target.c.inc | 25 +++++---- util/meson.build | 2 + 12 files changed, 189 insertions(+), 28 deletions(-) create mode 100644 host/include/loongarch64/host/atomic128-ldst.h create mode 100644 host/include/loongarch64/host/cpuinfo.h create mode 100644 host/include/loongarch64/host/load-extract-al16-al8.h create mode 100644 host/include/loongarch64/host/store-insert-al16.h create mode 100644 util/cpuinfo-loongarch.c Reviewed-by: WANG Xuerui