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Add LoongArch LASX instructions
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[RESEND,v5,00/57] Add LoongArch LASX instructions
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[RESEND,v5,01/57] target/loongarch: Renamed lsx*.c to vec* .c
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[RESEND,v5,02/57] target/loongarch: Implement gvec_*_vl functions
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[RESEND,v5,03/57] target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions
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[RESEND,v5,04/57] target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions
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[RESEND,v5,05/57] target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructions
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[RESEND,v5,06/57] target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructions
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[RESEND,v5,07/57] target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructions
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[RESEND,v5,08/57] target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructions
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[RESEND,v5,09/57] target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructions
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[RESEND,v5,10/57] target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)
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[RESEND,v5,11/57] target/loongarch: Add LASX data support
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[RESEND,v5,12/57] target/loongarch: check_vec support check LASX instructions
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[RESEND,v5,13/57] target/loongarch: Add avail_LASX to check LASX instructions
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[RESEND,v5,14/57] target/loongarch: Implement xvadd/xvsub
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[RESEND,v5,15/57] target/loongarch: Implement xvreplgr2vr
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[RESEND,v5,16/57] target/loongarch: Implement xvaddi/xvsubi
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[RESEND,v5,17/57] target/loongarch: Implement xvneg
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[RESEND,v5,18/57] target/loongarch: Implement xvsadd/xvssub
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[RESEND,v5,19/57] target/loongarch: Implement xvhaddw/xvhsubw
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[RESEND,v5,20/57] target/loongarch: Implement xvaddw/xvsubw
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[RESEND,v5,21/57] target/loongarch: Implement xavg/xvagr
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[RESEND,v5,22/57] target/loongarch: Implement xvabsd
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[RESEND,v5,23/57] target/loongarch: Implement xvadda
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[RESEND,v5,24/57] target/loongarch: Implement xvmax/xvmin
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[RESEND,v5,25/57] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}
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[RESEND,v5,26/57] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
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[RESEND,v5,27/57] target/loongarch; Implement xvdiv/xvmod
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[RESEND,v5,28/57] target/loongarch: Implement xvsat
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[RESEND,v5,29/57] target/loongarch: Implement xvexth
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[RESEND,v5,30/57] target/loongarch: Implement vext2xv
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[RESEND,v5,31/57] target/loongarch: Implement xvsigncov
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[RESEND,v5,32/57] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz
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[RESEND,v5,33/57] target/loognarch: Implement xvldi
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[RESEND,v5,34/57] target/loongarch: Implement LASX logic instructions
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[RESEND,v5,35/57] target/loongarch: Implement xvsll xvsrl xvsra xvrotr
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[RESEND,v5,36/57] target/loongarch: Implement xvsllwil xvextl
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[RESEND,v5,37/57] target/loongarch: Implement xvsrlr xvsrar
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[RESEND,v5,38/57] target/loongarch: Implement xvsrln xvsran
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[RESEND,v5,39/57] target/loongarch: Implement xvsrlrn xvsrarn
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[RESEND,v5,40/57] target/loongarch: Implement xvssrln xvssran
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[RESEND,v5,41/57] target/loongarch: Implement xvssrlrn xvssrarn
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[RESEND,v5,42/57] target/loongarch: Implement xvclo xvclz
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[RESEND,v5,43/57] target/loongarch: Implement xvpcnt
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[RESEND,v5,44/57] target/loongarch: Implement xvbitclr xvbitset xvbitrev
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[RESEND,v5,45/57] target/loongarch: Implement xvfrstp
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[RESEND,v5,46/57] target/loongarch: Implement LASX fpu arith instructions
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[RESEND,v5,47/57] target/loongarch: Implement LASX fpu fcvt instructions
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[RESEND,v5,48/57] target/loongarch: Implement xvseq xvsle xvslt
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[RESEND,v5,49/57] target/loongarch: Implement xvfcmp
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[RESEND,v5,50/57] target/loongarch: Implement xvbitsel xvset
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[RESEND,v5,51/57] target/loongarch: Implement xvinsgr2vr xvpickve2gr
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[RESEND,v5,52/57] target/loongarch: Implement xvreplve xvinsve0 xvpickve
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[RESEND,v5,53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h}
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[RESEND,v5,54/57] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i
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[RESEND,v5,55/57] target/loongarch: Implement xvld xvst
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[RESEND,v5,56/57] target/loongarch: Move simply DO_XX marcos togther
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[RESEND,v5,57/57] target/loongarch: CPUCFG support LASX
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