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([177.94.15.194]) by smtp.gmail.com with ESMTPSA id n21-20020a9d6f15000000b006b75242d6c3sm6229228otq.38.2023.09.06.02.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Sep 2023 02:16:53 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 00/19] riscv: split TCG/KVM accelerators from cpu.c Date: Wed, 6 Sep 2023 06:16:27 -0300 Message-ID: <20230906091647.1667171-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Based-on: 20230901194627.1214811-1-dbarboza@ventanamicro.com ("[PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG") Hi, This v2 contains changes suggested by Drew and Phil in v1. The series is now focused in the task at hand (split the accelerators), avoid changing existing behavior. The following v1 patches were dropped: - patches 5 and 6: the idea of having fine grained CPU behavior defined via class properties is too much for what we have today (generic CPUs, vendor CPUs and the 'host' KVM CPU). If we decide to add a forth CPU stereotype we can revisit this design - patches 19 and 20: partially for the same reason as we dropped patches 5 and 6. Second reason is that the design change disallowing vendor CPU support in KVM is too much to be tackled in this series and it deserves its separated thread Patch 13 was folded into patch 14. The forementioned changes left patch 13 with little changes to justify its own patch. Extra patches were created to attend suggestions that were a bit too much to do in the same patch. Patches missing acks: 5, 9, 10, 11, 14, 16 Changes from v1: - Dropped v1 patches: 5,6,19,20 - patch 13 from v1 folded patch 14 from v1, now known as patch 13. Commit msg from patch 14 was kept - patch 1: - added blank line after tcg_cpu_accel_type_info - patch 3: - added blank lines after each 'if' in riscv_cpu_validate_v() after moving it - patch 4: - removed "riscv_tcg_ops is being imported from cpu.c for now" comment - changed riscv_tcg_ops back to 'static' - patch 7 (former 9): - replaced "to minimize changes in the future" with "because they should not be modified at runtime" in the commit msg - patch 9 (new): - make riscv_add_satp_mode_properties() callable from kvm.c - patch 10 (new): - remove target/riscv/kvm-stub.c - add non-KVM stubs for APIs in kvm_riscv.h - patch 11: - remove the 'if kvm_enabled' block from riscv_cpu_add_user_properties() - patch 13 (former 14): - squashed together with patch 13 from v1. Commit msg from patch 14 was kept - make misa_bits[] zero-terminated - patch 14 (new): - export set_misa() as riscv_cpu_set_misa() - patch 16 (new): - make misa_ext_cfg[] const - patch 18 (former 17): - remove the 'make it const' reference in commit msg - v1 link: https://lore.kernel.org/qemu-riscv/20230901194627.1214811-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (19): target/riscv: introduce TCG AccelCPUClass target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c target/riscv: move riscv_tcg_ops to tcg-cpu.c target/riscv/cpu.c: add .instance_post_init() target/riscv: move 'host' CPU declaration to kvm.c target/riscv/cpu.c: mark extensions arrays as 'const' target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c target/riscv: make riscv_add_satp_mode_properties() public target/riscv: remove kvm-stub.c target/riscv: introduce KVM AccelCPUClass target/riscv: move KVM only files to kvm subdir target/riscv/kvm: do not use riscv_cpu_add_misa_properties() target/riscv/cpu.c: export set_misa() target/riscv/tcg: introduce tcg_cpu_instance_init() target/riscv/cpu.c: make misa_ext_cfgs[] 'const' target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c target/riscv/cpu.c: export isa_edata_arr[] target/riscv/cpu: move priv spec functions to tcg-cpu.c hw/intc/riscv_aplic.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 990 ++------------------------ target/riscv/cpu.h | 30 +- target/riscv/csr.c | 1 + target/riscv/kvm-stub.c | 30 - target/riscv/{kvm.c => kvm/kvm-cpu.c} | 120 +++- target/riscv/{ => kvm}/kvm_riscv.h | 27 +- target/riscv/kvm/meson.build | 1 + target/riscv/meson.build | 4 +- target/riscv/tcg/meson.build | 2 + target/riscv/tcg/tcg-cpu.c | 881 +++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.h | 28 + 13 files changed, 1138 insertions(+), 980 deletions(-) delete mode 100644 target/riscv/kvm-stub.c rename target/riscv/{kvm.c => kvm/kvm-cpu.c} (91%) rename target/riscv/{ => kvm}/kvm_riscv.h (64%) create mode 100644 target/riscv/kvm/meson.build create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/tcg-cpu.c create mode 100644 target/riscv/tcg/tcg-cpu.h