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Fri, 01 Sep 2023 12:46:33 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.94.15.194]) by smtp.gmail.com with ESMTPSA id h187-20020a4a5ec4000000b00565d41ba4d0sm2303002oob.35.2023.09.01.12.46.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Sep 2023 12:46:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG Date: Fri, 1 Sep 2023 16:46:06 -0300 Message-ID: <20230901194627.1214811-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, This new version contains suggestions made by Andrew Jones in v8. Most notable change is the removal of the opensbi.py test in patch 11, which was replaced by a TuxBoot test. It's more suitable to test the integrity of all the extensions enabled by the 'max' CPU. The series is available in this branch: https://gitlab.com/danielhb/qemu/-/tree/max_cpu_user_choice_v9 Patches missing acks: 11, 15 Changes from v8: - patch 7: - add g_assert(array) at the start of riscv_cpu_add_qdev_prop_array() - patch 8: - add g_assert(array) at the start of riscv_cpu_add_kvm_unavail_prop_array() - patch 11: - removed both opensbi.py tests - added 2 'max' cpu tuxboot tests in tuxrun_baselines.py - patch 12: - fixed typos in deprecated.rst - patch 15: - use g_assert_not_reached() at the end of cpu_cfg_ext_get_min_version() - patch 19: - added comment on top of riscv_cpu_add_misa_properties() explaining why we're not implementing user choice support for MISA properties - patch 20: - warn_report() is now called after the G error conditions - v8 link: https://lore.kernel.org/qemu-riscv/20230824221440.484675-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (20): target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] target/riscv/cpu.c: skip 'bool' check when filtering KVM props target/riscv/cpu.c: split kvm prop handling to its own helper target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() target/riscv/cpu.c: limit cfg->vext_spec log message target/riscv: add 'max' CPU type avocado, risc-v: add tuxboot tests for 'max' CPU target/riscv: deprecate the 'any' CPU type target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled target/riscv: make CPUCFG() macro public target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() target/riscv/cpu.c: consider user option with RVG docs/about/deprecated.rst | 12 + target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 564 +++++++++++++++++++++--------- target/riscv/cpu.h | 2 + target/riscv/kvm.c | 8 +- tests/avocado/tuxrun_baselines.py | 32 ++ 6 files changed, 450 insertions(+), 169 deletions(-)