From patchwork Tue Aug 22 03:27:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Song Gao X-Patchwork-Id: 1823851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4RVFGm41qyz1yNm for ; Tue, 22 Aug 2023 13:30:24 +1000 (AEST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qYI3R-0005oz-Eq; Mon, 21 Aug 2023 23:27:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qYI3Q-0005oM-2X for qemu-devel@nongnu.org; Mon, 21 Aug 2023 23:27:40 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qYI3K-00037J-S2 for qemu-devel@nongnu.org; Mon, 21 Aug 2023 23:27:39 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxZ+gdK+RkL8kaAA--.18795S3; Tue, 22 Aug 2023 11:27:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxF8wcK+RkYv5fAA--.63059S2; Tue, 22 Aug 2023 11:27:24 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, c@jia.je, philmd@linaro.org, maobibo@loongson.cn, yangxiaojuan@loongson.cn, yijun@loongson.cn, shenjinyang@loongson.cn Subject: [PATCH v4 00/15] Add some checks before translating instructions Date: Tue, 22 Aug 2023 11:27:09 +0800 Message-Id: <20230822032724.1353391-1-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxF8wcK+RkYv5fAA--.63059S2 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Based-on: https://patchew.org/QEMU/20230821125959.28666-1-philmd@linaro.org/ Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CPUCFG[2].LSPW CPUCFG[2].LAM CPUCFG[2].LSX And this series adds [1] patches together. Patch 9,10 need review. V4: - Rebase; - Split patch 'Add LoongArch32 cpu la132' in two patch; (PMD) - Remove unrelated cpucfgX;(PMD) - R-b. V3: - Rebase; - The la32 instructions following Table 2 at [2]. V2: - Add a check parameter to the TRANS macro. - remove TRANS_64. - Add avail_ALL/64/FP/FP_SP/FP_DP/LSPW/LAM/LSX/IOCSR to check instructions. [1]: https://patchew.org/QEMU/20230809083258.1787464-1-c@jia.je/ [2]: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Jiajie Chen (7): target/loongarch: Support LoongArch32 TLB entry target/loongarch: Support LoongArch32 DMW target/loongarch: Support LoongArch32 VPPN target/loongarch: Add LA64 & VA32 to DisasContext target/loongarch: Truncate high 32 bits of address in VA32 mode target/loongarch: Sign extend results in VA32 mode target/loongarch: Add LoongArch32 cpu la132 Song Gao (8): target/loongarch: Add a check parameter to the TRANS macro target/loongarch: Add avail_64 to check la64-only instructions hw/loongarch: Remove restriction of la464 cores in the virt machine target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions target/loongarch: Add avail_LSPW to check LSPW instructions target/loongarch: Add avail_LAM to check atomic instructions target/loongarch: Add avail_LSX to check LSX instructions target/loongarch: Add avail_IOCSR to check iocsr instructions target/loongarch/cpu-csr.h | 22 +- target/loongarch/cpu.h | 22 + target/loongarch/translate.h | 19 +- hw/loongarch/virt.c | 5 - target/loongarch/cpu.c | 46 +- target/loongarch/gdbstub.c | 2 +- target/loongarch/op_helper.c | 4 +- target/loongarch/tlb_helper.c | 66 +- target/loongarch/translate.c | 46 + target/loongarch/insn_trans/trans_arith.c.inc | 98 +- .../loongarch/insn_trans/trans_atomic.c.inc | 85 +- target/loongarch/insn_trans/trans_bit.c.inc | 56 +- .../loongarch/insn_trans/trans_branch.c.inc | 27 +- target/loongarch/insn_trans/trans_extra.c.inc | 24 +- .../loongarch/insn_trans/trans_farith.c.inc | 96 +- target/loongarch/insn_trans/trans_fcmp.c.inc | 8 + target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +- .../loongarch/insn_trans/trans_fmemory.c.inc | 62 +- target/loongarch/insn_trans/trans_fmov.c.inc | 52 +- target/loongarch/insn_trans/trans_lsx.c.inc | 1520 +++++++++-------- .../loongarch/insn_trans/trans_memory.c.inc | 118 +- .../insn_trans/trans_privileged.c.inc | 24 +- target/loongarch/insn_trans/trans_shift.c.inc | 34 +- 23 files changed, 1429 insertions(+), 1063 deletions(-)