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[176.182.122.208]) by smtp.gmail.com with ESMTPSA id a19-20020a05600c225300b003fee83ae4a3sm7216401wmm.9.2023.08.21.06.00.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 21 Aug 2023 06:00:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Song Gao , Jiajie Chen , Xiaojuan Yang , Huacai Chen Subject: [PATCH v3 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Date: Mon, 21 Aug 2023 14:59:51 +0200 Message-ID: <20230821125959.28666-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Series fully reviewed. v3: - Do not rename loongarch_la464_initfn (rth) - Added R-b v2: - Do no rename loongarch_cpu_get/set_pc (rth) - Rebased Jiajie's patches for convenience - Added rth's R-b Jiajie, this series contains few notes I took while reviewing your series adding loongarch32 support [*]. If your series isn't merged, consider rebasing it on this one. Regards, Phil. [*] https://lore.kernel.org/qemu-devel/20230817093121.1053890-1-gaosong@loongson.cn/ Jiajie Chen (3): target/loongarch: Add function to check current arch target/loongarch: Add new object class for loongarch32 cpus target/loongarch: Add GDB support for loongarch32 mode Philippe Mathieu-Daudé (4): target/loongarch: Log I/O write accesses to CSR registers target/loongarch: Remove duplicated disas_set_info assignment target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Song Gao (1): target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW configs/targets/loongarch64-softmmu.mak | 2 +- target/loongarch/cpu.h | 12 +++++ target/loongarch/cpu.c | 60 ++++++++++++++++++++----- target/loongarch/gdbstub.c | 32 ++++++++++--- gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++ 5 files changed, 131 insertions(+), 20 deletions(-) create mode 100644 gdb-xml/loongarch-base32.xml