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[189.69.160.189]) by smtp.gmail.com with ESMTPSA id v15-20020a0568301bcf00b006b94fb2762asm5526849ota.23.2023.08.15.13.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Aug 2023 13:36:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 0/8] riscv: detecting user choice in TCG extensions Date: Tue, 15 Aug 2023 17:36:27 -0300 Message-ID: <20230815203635.400179-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Based-on: 20230815201559.398643-1-dbarboza@ventanamicro.com Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, This new version is a rebase on top of the new version of the 'max' CPU series: [PATCH v7 00/12] riscv: add 'max' CPU, deprecate 'any' The changes made from v6 to v7 conflicted with the code from v1 of this series. No changes made aside from trivial conflicts. All patches acked. Changes from v1: - rebased on top of "[PATCH v7 00/12] riscv: add 'max' CPU, deprecate 'any'" - v1 link: https://lore.kernel.org/qemu-riscv/20230728131520.110394-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (8): target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled target/riscv: make CPUCFG() macro public target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() target/riscv/cpu.c: consider user option with RVG target/riscv/cpu.c | 400 +++++++++++++++++++++++++++++---------------- target/riscv/cpu.h | 2 + target/riscv/kvm.c | 8 +- 3 files changed, 266 insertions(+), 144 deletions(-)