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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH for-8.2 00/24] tcg: Introduce negsetcond opcodes Date: Mon, 7 Aug 2023 20:11:19 -0700 Message-Id: <20230808031143.50925-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce two new setcond opcode variants which produce -1 instead of 1 when the condition. For most of our hosts, producing -1 is just as easy as 1, and avoid requiring a separate negate instruction. Use the new opcode in tcg/tcg-op-gvec.c for integral expansion of generic vector operations. I looked through target/ for obvious pairings of setcond and neg. r~ Richard Henderson (24): tcg: Introduce negsetcond opcodes tcg: Use tcg_gen_negsetcond_* target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero target/arm: Use tcg_gen_negsetcond_* target/m68k: Use tcg_gen_negsetcond_* target/openrisc: Use tcg_gen_negsetcond_* target/ppc: Use tcg_gen_negsetcond_* target/sparc: Use tcg_gen_movcond_i64 in gen_edge target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl tcg/ppc: Implement negsetcond_* tcg/ppc: Use the Set Boolean Extension tcg/aarch64: Implement negsetcond_* tcg/arm: Implement negsetcond_i32 tcg/riscv: Implement negsetcond_* tcg/s390x: Implement negsetcond_* tcg/sparc64: Implement negsetcond_* tcg/i386: Merge tcg_out_brcond{32,64} tcg/i386: Merge tcg_out_setcond{32,64} tcg/i386: Merge tcg_out_movcond{32,64} tcg/i386: Add cf parameter to tcg_out_cmp tcg/i386: Use CMP+SBB in tcg_out_setcond tcg/i386: Clear dest first in tcg_out_setcond if possible tcg/i386: Use shift in tcg_out_setcond tcg/i386: Implement negsetcond_* docs/devel/tcg-ops.rst | 6 + include/tcg/tcg-op-common.h | 4 + include/tcg/tcg-op.h | 2 + include/tcg/tcg-opc.h | 2 + include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 2 + tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 + tcg/loongarch64/tcg-target.h | 3 + tcg/mips/tcg-target.h | 2 + tcg/ppc/tcg-target.h | 2 + tcg/riscv/tcg-target.h | 2 + tcg/s390x/tcg-target.h | 2 + tcg/sparc64/tcg-target.h | 2 + tcg/tci/tcg-target.h | 2 + target/alpha/translate.c | 7 +- target/arm/tcg/translate-a64.c | 22 +- target/arm/tcg/translate.c | 12 +- target/m68k/translate.c | 24 +- target/openrisc/translate.c | 6 +- target/sparc/translate.c | 17 +- target/tricore/translate.c | 16 +- tcg/optimize.c | 41 +++- tcg/tcg-op-gvec.c | 6 +- tcg/tcg-op.c | 42 +++- tcg/tcg.c | 6 + target/ppc/translate/fixedpoint-impl.c.inc | 6 +- target/ppc/translate/vmx-impl.c.inc | 8 +- tcg/aarch64/tcg-target.c.inc | 12 + tcg/arm/tcg-target.c.inc | 9 + tcg/i386/tcg-target.c.inc | 265 +++++++++++++-------- tcg/ppc/tcg-target.c.inc | 149 ++++++++---- tcg/riscv/tcg-target.c.inc | 45 ++++ tcg/s390x/tcg-target.c.inc | 78 ++++-- tcg/sparc64/tcg-target.c.inc | 36 ++- 35 files changed, 572 insertions(+), 270 deletions(-)