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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:15 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 00/15] target/arm/ptw: Cleanups and a few bugfixes Date: Mon, 7 Aug 2023 15:14:59 +0100 Message-Id: <20230807141514.19075-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org While I was fixing a ptw bug recently, I noticed that we had a somewhat confusing mix of ptw->in_space and ptw->in_secure, where in theory the two are supposed to be in sync and you can figure out the in_secure state from the in_space. This patch series' principal aim is to clean that up by removing the in_secure and out_secure fields in the S1Translate struct. The first three patches are fixes for (minor) bugs I noticed while I was trying to do this refactoring because they're in or around places that were using in_secure. The next four are basically plumbing: passing ARMSecurityState arguments instead of boolean is_secure arguments. The next four patches then can get rid of uses of the in_secure and out_secure fields and drop them entirely. Finally, the last four patches are minor bug fixes for various corner cases that I noticed while I was testing this. Changes v1->v2: * in patch 6, avoid calling arm_hcr_el2_eff_secstate() with ARMSS_Root, rather than making it return 0 * new patch 7 ("Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate()") Only patches 6 and 7 still need review. thanks -- PMM Peter Maydell (15): target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults target/arm/ptw: Set s1ns bit in fault info more consistently target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled() target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled() target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate() target/arm/ptw: Only fold in NSTable bit effects in Secure state target/arm/ptw: Remove last uses of ptw->in_secure target/arm/ptw: Remove S1Translate::in_secure target/arm/ptw: Drop S1Translate::out_secure target/arm/ptw: Set attributes correctly for MMU disabled data accesses target/arm/ptw: Check for block descriptors at invalid levels target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types target/arm/cpu.h | 15 ++-- target/arm/helper.c | 23 +++++- target/arm/ptw.c | 192 +++++++++++++++++++++++++++----------------- 3 files changed, 146 insertions(+), 84 deletions(-)