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[RESEND,v3,0/1] target/riscv: Add Zihintntl extension ISA string to DTS

Message ID 20230726074049.19505-1-jason.chien@sifive.com
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Series [RESEND,v3,1/1] target/riscv: Add Zihintntl extension ISA string to DTS | expand

Message

Jason Chien July 26, 2023, 7:40 a.m. UTC 
In v2, I rebased the patch on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
However, I forgot to add "Reviewed-by" in v2, so I add them in v3.

Jason Chien (1):
  target/riscv: Add Zihintntl extension ISA string to DTS

 target/riscv/cpu.c     | 2 ++
 target/riscv/cpu_cfg.h | 1 +
 2 files changed, 3 insertions(+)