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[for-8.2,v2,0/7] target/riscv: add 'max' CPU type

Message ID 20230712205748.446931-1-dbarboza@ventanamicro.com
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Series target/riscv: add 'max' CPU type | expand

Message

Daniel Henrique Barboza July 12, 2023, 8:57 p.m. UTC 
Hi,

This second version has smalls tweak in patch 6 that I found out
missing while chatting with Conor in the v1 review.

Changes from v1:
- patch 6:
  - enable RVG, RVJ and RVV in riscv_init_max_cpu_extensions()
  - Added the resulting 'riscv,isa' DT in the commit message
- v1 link: https://lore.kernel.org/qemu-riscv/20230712190149.424675-1-dbarboza@ventanamicro.com/T/#t


Daniel Henrique Barboza (7):
  target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]
  target/riscv/cpu.c: skip 'bool' check when filtering KVM props
  target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]
  target/riscv/cpu.c: split non-ratified exts from
    riscv_cpu_extensions[]
  target/riscv/cpu.c: add a ADD_CPU_PROPERTIES_ARRAY() macro
  target/riscv: add 'max' CPU type
  avocado, risc-v: add opensbi tests for 'max' CPU

 target/riscv/cpu-qom.h         |   1 +
 target/riscv/cpu.c             | 109 +++++++++++++++++++++++++++------
 tests/avocado/riscv_opensbi.py |  16 +++++
 3 files changed, 106 insertions(+), 20 deletions(-)