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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a10-20020adfeeca000000b00314103d6daesm15834737wrp.47.2023.07.04.06.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 06:06:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/2] target/arm: Implement Cortex Neoverse-V1 Date: Tue, 4 Jul 2023 14:06:45 +0100 Message-Id: <20230704130647.2842917-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patchset implements the Cortex Neoverse-V1 CPU type, as a representative Armv8.3 (+ some extras from 8.4) CPU matching real hardware. The main thing we were waiting for to be able to define this was FEAT_LSE2, and that is now supported. There are a few things the real hardware implements that QEMU does not yet, which patch 1 ensures we don't advertise to the guest: * FEAT_TRF (Self-hosted Trace Extension) * Trace Macrocell system register access * Memory mapped trace * FEAT_AMU (Activity Monitors Extension) * FEAT_MPAM (Memory Partitioning and Monitoring Extension) * FEAT_NV (Nested Virtualization) Most of these, like FEAT_SPE which we were already suppressing, are "introspection/trace" type features which QEMU is unlikely to ever implement. The odd-one-out here is FEAT_NV -- we could implement that and at some point we probably will. Patch 2 then implements the CPU itself. thanks -- PMM Peter Maydell (2): target/arm: Suppress more TCG unimplemented features in ID registers target/arm: Define neoverse-v1 docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu.c | 33 ++++++++-- target/arm/tcg/cpu64.c | 128 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 160 insertions(+), 4 deletions(-) Tested-by: Marcin Juszkiewicz