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[RFC,0/3] ppc/pnv: SMT support for powernv

Message ID 20230629021633.328916-1-npiggin@gmail.com
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Series ppc/pnv: SMT support for powernv | expand

Message

Nicholas Piggin June 29, 2023, 2:16 a.m. UTC 
These patches implement enough to boot a SMT powernv machine to Linux
and boot a SMP KVM guest inside that.

There are a few more SPRs that need to be done, and per-LPAR SPRs are
mostly not annotated yet so it can't run in 1LPAR mode. But it is
enough to run skiboot/Linux with SMT so I'll just post the minimal
patches for RFC because the concept isn't really different to add
more SPRs and things.

Thanks,
Nick

Nicholas Piggin (3):
  target/ppc: Add LPAR-per-core vs per-thread mode flag
  target/ppc: SMT support for the HID SPR
  ppc/pnv: SMT support for powernv

 hw/ppc/pnv.c             | 12 ++++++++++++
 hw/ppc/pnv_core.c        | 13 +++++--------
 hw/ppc/spapr_cpu_core.c  |  2 ++
 target/ppc/cpu.h         |  3 +++
 target/ppc/cpu_init.c    | 14 +++++++++++++-
 target/ppc/helper.h      |  1 +
 target/ppc/misc_helper.c | 21 +++++++++++++++++++++
 target/ppc/spr_common.h  |  1 +
 target/ppc/translate.c   | 32 +++++++++++++++++++++++++++++---
 9 files changed, 87 insertions(+), 12 deletions(-)

Comments

Cédric Le Goater June 29, 2023, 6:28 a.m. UTC | #1 
On 6/29/23 04:16, Nicholas Piggin wrote:
> These patches implement enough to boot a SMT powernv machine to Linux
> and boot a SMP KVM guest inside that.
> 
> There are a few more SPRs that need to be done, and per-LPAR SPRs are
> mostly not annotated yet so it can't run in 1LPAR mode. But it is
> enough to run skiboot/Linux with SMT so I'll just post the minimal
> patches for RFC because the concept isn't really different to add
> more SPRs and things.

This is good material for 8.1. Please send a v1 and Cc: all pnv reviewers.

Thanks,

C.
Cédric Le Goater June 29, 2023, 7:59 a.m. UTC | #2 
On 6/29/23 04:16, Nicholas Piggin wrote:
> These patches implement enough to boot a SMT powernv machine to Linux
> and boot a SMP KVM guest inside that.
> 
> There are a few more SPRs that need to be done, and per-LPAR SPRs are
> mostly not annotated yet so it can't run in 1LPAR mode. But it is
> enough to run skiboot/Linux with SMT so I'll just post the minimal
> patches for RFC because the concept isn't really different to add
> more SPRs and things.
> 
> Thanks,
> Nick

QEMU could boot a 2 sockets x 2 cores x 4 threads machine with MTTCG
in less than a minute. Very nice :)

Thanks,

C.

root@jammy:~# lscpu
Architecture:          ppc64le
   Byte Order:          Little Endian
CPU(s):                16
   On-line CPU(s) list: 0-15
Model name:            POWER9, altivec supported
   Model:               2.2 (pvr 004e 1202)
   Thread(s) per core:  4
   Core(s) per socket:  2
   Socket(s):           2
Caches (sum of all):
   L1d:                 128 KiB (4 instances)
   L1i:                 128 KiB (4 instances)
NUMA:
   NUMA node(s):        2
   NUMA node0 CPU(s):   0-7
   NUMA node1 CPU(s):   8-15




> Nicholas Piggin (3):
>    target/ppc: Add LPAR-per-core vs per-thread mode flag
>    target/ppc: SMT support for the HID SPR
>    ppc/pnv: SMT support for powernv
> 
>   hw/ppc/pnv.c             | 12 ++++++++++++
>   hw/ppc/pnv_core.c        | 13 +++++--------
>   hw/ppc/spapr_cpu_core.c  |  2 ++
>   target/ppc/cpu.h         |  3 +++
>   target/ppc/cpu_init.c    | 14 +++++++++++++-
>   target/ppc/helper.h      |  1 +
>   target/ppc/misc_helper.c | 21 +++++++++++++++++++++
>   target/ppc/spr_common.h  |  1 +
>   target/ppc/translate.c   | 32 +++++++++++++++++++++++++++++---
>   9 files changed, 87 insertions(+), 12 deletions(-)
>