| Message ID | 20230508075859.3326566-1-clg@kaod.org |
|---|---|
| Headers | show |
| Series | aspeed: fixes and extensions | expand |
Hello, On 5/8/23 09:58, Cédric Le Goater wrote: > Hello, > > This series fixes issues spotted by Coverity and adds a couple of > improvements for the machine definition. > > The first is to offer the capability to define all CS of all SPI > controllers without introducing new machine types, using a blockdev on > the command line : > > -blockdev node-name=fmc0,driver=file,filename=./flash.img > -device mx66u51235f,addr=0x0,bus=ssi.0,drive=fmc0 > > instead of using drives which relies on the command line order. > Ultimately, we will get rid of drive_get(IF_MTD, ...) but we are not > there yet. For this, SSIPeripheral is extended with an "addr" > property. > > A second extension is the introduction of a "uart" machine option to > let the user define the default UART device of the machine from the > QEMU command line : > > -M ast2500-evb,uart=uart3 > > Last, a new "vfp-d32" CPU property is added to ARM CPUs to model FPUs > implementing VFPv4 without NEON support and with 16 64-bit FPU > registers (and not 32 registers). This is the case for the Cortex A7 > of the Aspeed AST2600 SoC. I hope I got it right this time. I should include these changes in the next aspeed PR. I would have preferred to have R-b tags on some of them, SSI for instance, and also the last patch adding the "vfp-d32" CPU property. Thanks, C.
Hello, This series fixes issues spotted by Coverity and adds a couple of improvements for the machine definition. The first is to offer the capability to define all CS of all SPI controllers without introducing new machine types, using a blockdev on the command line : -blockdev node-name=fmc0,driver=file,filename=./flash.img -device mx66u51235f,addr=0x0,bus=ssi.0,drive=fmc0 instead of using drives which relies on the command line order. Ultimately, we will get rid of drive_get(IF_MTD, ...) but we are not there yet. For this, SSIPeripheral is extended with an "addr" property. A second extension is the introduction of a "uart" machine option to let the user define the default UART device of the machine from the QEMU command line : -M ast2500-evb,uart=uart3 Last, a new "vfp-d32" CPU property is added to ARM CPUs to model FPUs implementing VFPv4 without NEON support and with 16 64-bit FPU registers (and not 32 registers). This is the case for the Cortex A7 of the Aspeed AST2600 SoC. I hope I got it right this time. Thanks, C. Cédric Le Goater (12): aspeed/hace: Initialize g_autofree pointer aspeed: Introduce a boot_rom region at the machine level aspeed: Use the boot_rom region of the fby35 machine hw/ssi: Add an "addr" property to SSIPeripheral hw/ssi: Introduce a ssi_get_cs() helper aspeed/smc: Wire CS lines at reset hw/ssi: Check for duplicate addresses aspeed: Create flash devices only when defaults are enabled m25p80: Introduce an helper to retrieve the BlockBackend of a device aspeed: Get the BlockBackend of FMC0 from the flash device aspeed: Introduce a "uart" machine option target/arm: Allow users to set the number of VFP registers docs/system/arm/aspeed.rst | 10 +++++ include/hw/block/flash.h | 4 ++ include/hw/ssi/ssi.h | 5 +++ target/arm/cpu.h | 2 + hw/arm/aspeed.c | 68 ++++++++++++++++++++++------- hw/arm/aspeed_ast2600.c | 2 + hw/arm/fby35.c | 29 ++++++------ hw/arm/stellaris.c | 4 +- hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/arm/xlnx-zcu102.c | 2 + hw/block/m25p80.c | 6 +++ hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/misc/aspeed_hace.c | 2 +- hw/ssi/aspeed_smc.c | 8 ++++ hw/ssi/ssi.c | 42 ++++++++++++++++++ target/arm/cpu.c | 32 ++++++++++++++ 17 files changed, 187 insertions(+), 32 deletions(-)