| Message ID | 20230213180215.1524938-1-bmeng@tinylab.org |
|---|---|
| Headers | show |
| Series | target/riscv: Various fixes to gdbstub and CSR access | expand |
Bin, I received only patches 1-11. I don't see the remaining patches in patchwork: https://patchwork.kernel.org/project/qemu-devel/list/?series=721372 or in the qemu-devel archives: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg03461.html Can you please verify? Thanks, Daniel On 2/13/23 15:01, Bin Meng wrote: > At present gdbstub reports an incorrect / incomplete CSR list in the > target description XML, for example: > > - menvcfg is reported in 'sifive_u' machine > - fcsr is missing in a F/D enabled processor > > The issue is caused by: > - priv spec version check is missing when reporting CSRs > - CSR predicate() routine is called without turning on the debugger flag > > This series aims to generate a correct and complete CSR list for gdbstub. > > > Bin Meng (18): > target/riscv: gdbstub: Check priv spec version before reporting CSR > target/riscv: Correct the priority policy of riscv_csrrw_check() > target/riscv: gdbstub: Minor change for better readability > target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled > target/riscv: Coding style fixes in csr.c > target/riscv: Use 'bool' type for read_only > target/riscv: Simplify {read,write}_pmpcfg() a little bit > target/riscv: Simplify getting RISCVCPU pointer from env > target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for > RV64 > target/riscv: gdbstub: Turn on debugger mode before calling CSR > predicate() > target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml > target/riscv: Allow debugger to access user timer and counter CSRs > target/riscv: Allow debugger to access seed CSR > target/riscv: Allow debugger to access {h,s}stateen CSRs > target/riscv: Allow debugger to access sstc CSRs > target/riscv: Drop priv level check in mseccfg predicate() > target/riscv: Group all predicate() routines together > target/riscv: Move configuration check to envcfg CSRs predicate() > > target/riscv/csr.c | 360 +++++++++++++++++++++++------------------ > target/riscv/gdbstub.c | 100 +++--------- > 2 files changed, 221 insertions(+), 239 deletions(-) >
Hi Daniel, On Tue, Feb 14, 2023 at 3:20 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Bin, > > > I received only patches 1-11. I don't see the remaining patches in patchwork: > > > https://patchwork.kernel.org/project/qemu-devel/list/?series=721372 > > > or in the qemu-devel archives: > > > https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg03461.html > > > Can you please verify? Thanks, > Somehow my email service provider blocked some of my patches. I've now resent the missing patches, and I just verified that it showed up in the patchwork. Regards, Bin
At present gdbstub reports an incorrect / incomplete CSR list in the target description XML, for example: - menvcfg is reported in 'sifive_u' machine - fcsr is missing in a F/D enabled processor The issue is caused by: - priv spec version check is missing when reporting CSRs - CSR predicate() routine is called without turning on the debugger flag This series aims to generate a correct and complete CSR list for gdbstub. Bin Meng (18): target/riscv: gdbstub: Check priv spec version before reporting CSR target/riscv: Correct the priority policy of riscv_csrrw_check() target/riscv: gdbstub: Minor change for better readability target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled target/riscv: Coding style fixes in csr.c target/riscv: Use 'bool' type for read_only target/riscv: Simplify {read,write}_pmpcfg() a little bit target/riscv: Simplify getting RISCVCPU pointer from env target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml target/riscv: Allow debugger to access user timer and counter CSRs target/riscv: Allow debugger to access seed CSR target/riscv: Allow debugger to access {h,s}stateen CSRs target/riscv: Allow debugger to access sstc CSRs target/riscv: Drop priv level check in mseccfg predicate() target/riscv: Group all predicate() routines together target/riscv: Move configuration check to envcfg CSRs predicate() target/riscv/csr.c | 360 +++++++++++++++++++++++------------------ target/riscv/gdbstub.c | 100 +++--------- 2 files changed, 221 insertions(+), 239 deletions(-)