mbox series

[00/11] enable write_misa() and RISCV_FEATURE_* cleanups

Message ID 20230210133635.589647-1-dbarboza@ventanamicro.com
Headers show
Series enable write_misa() and RISCV_FEATURE_* cleanups | expand

Message

Daniel Henrique Barboza Feb. 10, 2023, 1:36 p.m. UTC 
Hi,

Initially this was supposed to be just the first 2 patches, where we
enable users to be able to actually write the MISA CSR (yes, at this
moment all the code in write_misa() is a no-op).

During an internal discussion of that code, Andrew Jones pointed out
that I was setting RISCV_FEATURE_MISA by just mirroring the value
already set in cpu->cfg.misa_w, and asked why that was necessary.
Instead of replying "I'm doing it because it's being done for every
other feature in that enum" - which was the truth - I decided to take a
closer look.

The RISCV_FEATURES_* enum and the CPUArchState::features attribute were
introduced 4+ years ago, as a way to retrieve the enabled hart features
that aren't represented via MISA CSR bits. Time passed on, and
RISCVCPUConfig was introduced. With it, we now have a centralized way of
reading all hart features that are enabled/disabled by the user and the
board. All recent features are reading their correspondent cpu->cfg.X
flag.

All but the 5 features in the RISCV_FEATURE_* enum. These features are
still operating in the same way: set it during riscv_cpu_realize() using
their cpu->cfg value, read it using riscv_feature() when needed. There
is nothing special about them in comparison with all the other features
and extensions to justify this special handling.

This series then is doing two things: first we're actually allowing
users to write the MISA CSR if they so choose. Then we're deprecate each
RISC_FEATURE_* usage until, in patch 11, we remove everything related to
it. All 5 existing RISCV_FEATURE_* features will be handled as everyone
else. 

Note: patch 6 is adding an error message that will fire a checkpatch.pl
warning (82 chars). The following patch will put the error message back
into the acceptable 80 chars range. 

Daniel Henrique Barboza (11):
  target/riscv: do not mask unsupported QEMU extensions in write_misa()
  target/riscv: allow users to actually write the MISA CSR
  target/riscv: remove RISCV_FEATURE_MISA
  target/riscv: introduce riscv_cpu_cfg()
  target/riscv: remove RISCV_FEATURE_DEBUG
  target/riscv/cpu.c: error out if EPMP is enabled without PMP
  target/riscv: remove RISCV_FEATURE_EPMP
  target/riscv: remove RISCV_FEATURE_PMP
  hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in
    create_fdt_socket_cpus()
  target/riscv: remove RISCV_FEATURE_MMU
  target/riscv/cpu: remove CPUArchState::features and friends

 hw/riscv/virt.c           |  7 ++++---
 target/riscv/cpu.c        | 20 +++++---------------
 target/riscv/cpu.h        | 29 ++++++-----------------------
 target/riscv/cpu_helper.c |  6 +++---
 target/riscv/csr.c        | 17 ++++++++---------
 target/riscv/machine.c    | 11 ++++-------
 target/riscv/monitor.c    |  2 +-
 target/riscv/op_helper.c  |  2 +-
 target/riscv/pmp.c        |  8 ++++----
 9 files changed, 36 insertions(+), 66 deletions(-)