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Mon, 06 Feb 2023 14:35:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Laurent Vivier , Richard Henderson , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 00/11] target/arm: Housekeeping around NVIC Date: Mon, 6 Feb 2023 23:34:51 +0100 Message-Id: <20230206223502.25122-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Missing review: 1-3, 5, 9-10 Few cleanups while using link properties between CPU/NVIC: - Simplify ID_PFR1 on useremu - Move NVIC helpers to "hw/intc/armv7m_nvic.h" Since v1: addressed Richard's reviews - Do not restrict v7-M MMU helpers to TCG sysemu since they can be used for user-emu. Hardcode ARMMMUIdx_MUser - Convert CPUARMState::eabi to boolean - Split 'Restrict nvic to sysemu and store as NVICState' in 3 patches - Dropped following (RFC) patches: - neg_prio_requested / unrealized property problem - use object_property_add_const_link() Philippe Mathieu-Daudé (11): hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope target/arm: Constify ID_PFR1 on user emulation target/arm: Convert CPUARMState::eabi to boolean target/arm: Avoid resetting CPUARMState::eabi field target/arm: Restrict CPUARMState::gicv3state to sysemu target/arm: Restrict CPUARMState::arm_boot_info to sysemu target/arm: Restrict CPUARMState::nvic to sysemu target/arm: Store CPUARMState::nvic as NVICState* target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' hw/intc/armv7m_nvic.c | 38 ++++------ include/hw/intc/armv7m_nvic.h | 128 ++++++++++++++++++++++++++++++- linux-user/arm/cpu_loop.c | 4 +- linux-user/user-internals.h | 2 +- target/arm/cpu.c | 5 +- target/arm/cpu.h | 137 ++-------------------------------- target/arm/cpu_tcg.c | 3 + target/arm/helper.c | 12 ++- target/arm/internals.h | 14 ---- target/arm/m_helper.c | 86 +++++++++++---------- 10 files changed, 212 insertions(+), 217 deletions(-)