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([191.19.125.138]) by smtp.gmail.com with ESMTPSA id s13-20020a0568080b0d00b00364e8f85c08sm4151177oij.21.2023.02.06.06.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Feb 2023 06:00:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v11 0/3] Consolidate all kernel init in load_kernel() Date: Mon, 6 Feb 2023 11:00:19 -0300 Message-Id: <20230206140022.2748401-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hi, In this new version patch 1 was changed to extract the lower 32 bits of the 64 bit address when running 32 bit CPUs. The difference now, in comparison with what was being done in version 6, is that now we're doing that for all uses of kernel_entry, not just the one resulting from load_elf_ram_sym(). This will ensure that the current behavior, that is now based on the fact that load_initrd() uses the target_ulong returned by load_kernel(), that happens to be a 32 bit var when running in 32 bit targets, is preserved by doing a explicit 32 bit extract of the uint64_t kernel_entry for 32 bit CPUs. Changes in v10: - patch 1: - extract the lower 32 bits of kernel_entry for all cases, not just the one from load_elf_ram_sym(). - v10 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg00529.html Daniel Henrique Barboza (3): hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 97 ++++++++++++++++++++++++-------------- hw/riscv/microchip_pfsoc.c | 12 +---- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 12 +---- hw/riscv/spike.c | 14 ++---- hw/riscv/virt.c | 12 +---- include/hw/riscv/boot.h | 3 +- 8 files changed, 78 insertions(+), 80 deletions(-)