Message ID | 20230131180158.2471047-1-christoph.muellner@vrull.eu |
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Headers | show
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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:01 -0800 (PST) From: Christoph Muellner <christoph.muellner@vrull.eu> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Philipp Tomsich <philipp.tomsich@vrull.eu>, =?utf-8?q?Heiko_St=C3=BCbner?= <heiko.stuebner@vrull.eu>, Palmer Dabbelt <palmer@dabbelt.com>, Richard Henderson <richard.henderson@linaro.org>, Kito Cheng <kito.cheng@sifive.com>, Cooper Qu <cooper.qu@linux.alibaba.com>, Lifang Xia <lifang_xia@linux.alibaba.com>, Yunhai Shang <yunhai@linux.alibaba.com>, Zhiwei Liu <zhiwei_liu@linux.alibaba.com> Cc: =?utf-8?q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu> Subject: [PATCH v4 00/14] Add support for the T-Head vendor extensions Date: Tue, 31 Jan 2023 19:01:44 +0100 Message-Id: <20230131180158.2471047-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org |
Series |
Add support for the T-Head vendor extensions
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From: Christoph Müllner <christoph.muellner@vrull.eu> This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/latest The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. To enable the extensions above, the following two methods are possible: * add the extension to the arch string E.g. QEMU_CPU="any,xtheadcmo=true,xtheadsync=true" * implicitly select the extensions via CPU selection E.g. QEMU_CPU="thead-c906" Major changes in v2: - Add ISA_EXT_DATA_ENTRY()s - Use single decoder for XThead extensions - Simplify a lot of translation functions - Fix RV32 behaviour - Added XTheadFmv - Addressed all comments of v1 Major changes in v3: - Drop XMAE patch - Rename priv level test macros Changes in v4: - Address review comments from Richard Henderson Christoph Müllner (14): RISC-V: Adding XTheadCmo ISA extension RISC-V: Adding XTheadSync ISA extension RISC-V: Adding XTheadBa ISA extension RISC-V: Adding XTheadBb ISA extension RISC-V: Adding XTheadBs ISA extension RISC-V: Adding XTheadCondMov ISA extension RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Set minimum priv version for Zfh to 1.11 RISC-V: Add initial support for T-Head C906 RISC-V: Adding XTheadFmv ISA extension target/riscv: add a MAINTAINERS entry for XThead* extension support MAINTAINERS | 8 + target/riscv/cpu.c | 55 +- target/riscv/cpu.h | 12 + target/riscv/cpu_vendorid.h | 6 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 1100 ++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/op_helper.c | 6 + target/riscv/translate.c | 31 + target/riscv/xthead.decode | 185 ++++ 10 files changed, 1404 insertions(+), 1 deletion(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode