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Thu, 29 Dec 2022 07:23:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Steven Lee , Peter Delevoryas , Peter Delevoryas , qemu-arm@nongnu.org, Cleber Rosa , Peter Maydell , Beraldo Leal , Wainer dos Santos Moschetta , Troy Lee , Andrew Jeffery , Joel Stanley , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Delevoryas , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jamin Lin Subject: [PATCH 0/9] hw/arm/aspeed_ast10x0: Map more peripherals & few more fixes Date: Thu, 29 Dec 2022 16:23:16 +0100 Message-Id: <20221229152325.32041-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Trying to fix some bugs triggered running Zephyr. Still 2 bugs: 1/ uart:~$ sensor get SYSCLK [00:00:23.592,000] os: ***** USAGE FAULT ***** [00:00:23.593,000] os: Illegal use of the EPSR [00:00:23.593,000] os: r0/a1: 0x00033448 r1/a2: 0x00000000 r2/a3: 0x00047f50 [00:00:23.593,000] os: r3/a4: 0x00000000 r12/ip: 0x00000000 r14/lr: 0x00000fbd [00:00:23.593,000] os: xpsr: 0x60000000 [00:00:23.593,000] os: Faulting instruction address (r15/pc): 0x00000000 [00:00:23.593,000] os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0 [00:00:23.594,000] os: Current thread: 0x38248 (shell_uart) [00:00:23.601,000] os: Halting system 2/ uart:~$ mcuboot [00:01:04.990,000] os: ***** BUS FAULT ***** [00:01:04.990,000] os: Instruction bus error [00:01:04.991,000] os: r0/a1: 0x00000000 r1/a2: 0x000ffff0 r2/a3: 0x00047ef0 [00:01:04.991,000] os: r3/a4: 0x00000010 r12/ip: 0x6df7ecb5 r14/lr: 0x000188ed [00:01:04.991,000] os: xpsr: 0x61000000 [00:01:04.991,000] os: Faulting instruction address (r15/pc): 0x6df7ecb4 [00:01:04.991,000] os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0 [00:01:04.991,000] os: Current thread: 0x38248 (shell_uart) [00:01:04.994,000] os: Halting system ---------------- IN: PMSA MPU lookup for reading at 0x0001d400 mmu_idx 65 -> Hit (prot rwx) 0x0001d5a2: 6869 ldr r1, [r5, #4] 0x0001d5a4: 4421 add r1, r4 0x0001d5a6: 6883 ldr r3, [r0, #8] 0x0001d5a8: 681c ldr r4, [r3] 0x0001d5aa: 463a mov r2, r7 0x0001d5ac: 4633 mov r3, r6 0x0001d5ae: 46a4 mov ip, r4 0x0001d5b0: e8bd 41f0 pop.w {r4, r5, r6, r7, r8, lr} 0x0001d5b4: 4760 bx ip PMSA MPU lookup for reading at 0x00000008 mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for execute at 0x6df7ecb4 mmu_idx 65 -> Hit (prot rwx) Taking exception 3 [Prefetch Abort] on CPU 0 ...at fault address 0x6df7ecb4 ...with CFSR.IBUSERR PMSA MPU lookup for writing at 0x00047ec8 mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047ecc mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047ed0 mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047ed4 mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047ed8 mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047edc mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047ee0 mmu_idx 65 -> Hit (prot rwx) PMSA MPU lookup for writing at 0x00047ee4 mmu_idx 65 -> Hit (prot rwx) ...taking pending nonsecure exception 5 ...loading from element 5 of non-secure vector table at 0x14 ...loaded new PC 0xa0cd ---------------- HACE isn't really functional there. I probably screwed smth while wiring the peripheral. Not obvious without access to the datasheet. Philippe Mathieu-Daudé (9): hw/watchdog/wdt_aspeed: Map the whole MMIO range hw/arm/aspeed: Use the IEC binary prefix definitions hw/arm/aspeed_ast10x0: Add various unimplemented peripherals hw/arm/aspeed_ast10x0: Map I3C peripheral hw/arm/aspeed_ast10x0: Map the secure SRAM hw/arm/aspeed_ast10x0: Map HACE peripheral hw/misc/aspeed_hace: Do not crash if address_space_map() failed hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board hw/arm/aspeed_ast10x0.c | 84 ++++++++++++++++++++++++++++++-- hw/arm/aspeed_ast2600.c | 5 +- hw/arm/aspeed_soc.c | 6 +-- hw/misc/aspeed_hace.c | 21 +++++--- hw/watchdog/wdt_aspeed.c | 12 +++-- include/hw/arm/aspeed_soc.h | 14 ++++++ include/hw/watchdog/wdt_aspeed.h | 2 +- tests/avocado/machine_aspeed.py | 41 +++++++++++++++- 8 files changed, 163 insertions(+), 22 deletions(-)