From patchwork Sat Dec 24 02:02:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tianrui Zhao X-Patchwork-Id: 1719270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Nf6m541C8z1ydd for ; Sat, 24 Dec 2022 13:03:49 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p8trs-0006SD-3C; Fri, 23 Dec 2022 21:02:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p8trl-0006Rd-D2 for qemu-devel@nongnu.org; Fri, 23 Dec 2022 21:02:25 -0500 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p8tri-0002jD-FN for qemu-devel@nongnu.org; Fri, 23 Dec 2022 21:02:24 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Cx7+upXaZjlUAIAA--.18581S3; Sat, 24 Dec 2022 10:02:17 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxrb6oXaZjpoQKAA--.12484S2; Sat, 24 Dec 2022 10:02:16 +0800 (CST) From: Tianrui Zhao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, gaosong@loongson.cn, maobibo@loongson.cn, philmd@linaro.org Subject: [PATCH v3 0/2] Add irq number property for loongarch pch interrupt controller Date: Sat, 24 Dec 2022 10:02:14 +0800 Message-Id: <20221224020216.4142799-1-zhaotianrui@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dxrb6oXaZjpoQKAA--.12484S2 X-CM-SenderInfo: p2kd03xldq233l6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBjvdXoW7Xr1rGrWxAw1kAr1rZF1xAFb_yoWDCrc_uF yfJryUGw47XFy5KayUtFn3ArWUAa1rtFnxAF9FqF43GrnrJr15Jw4DWryrZrykKrWDX34F krWkKw1Fyr12kjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8wcxFpf9Il3svdxBIdaVrn0 xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3UjIYCTnIWjp_UUU5 37CY07I20VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4 vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7Cj xVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x 0267AKxVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E 6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x8ErcxFaVAv8VWrMcvjeVCFs4IE7x kEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCF04k20xvE74AGY7Cv 6cx26rWl4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x 8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE 2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42 xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF 7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0zRVWlkUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=zhaotianrui@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This series add irq number property for loongarch pch_msi and pch_pic interrupt controller. Changes for v3: (1) Fix the valid range of msi_irq_num, it will trigger error_setg() when irq_num is invalid. (2) Using g_new() to alloc msi_irqs when pch_msi realize. (3) Using EXTIOI_IRQS macro to replace the 256 irq number. Changes for v2: (1) Free pch_msi_irq array in pch_msi_unrealize(). Changes for v1: (1) Add irq number property for loongarch_pch_msi. (2) Add irq number property for loongarch_pch_pic. Tianrui Zhao (2): hw/intc/loongarch_pch_msi: add irq number property hw/intc/loongarch_pch_pic: add irq number property hw/intc/loongarch_pch_msi.c | 33 ++++++++++++++++++++++++++--- hw/intc/loongarch_pch_pic.c | 29 +++++++++++++++++++++---- hw/loongarch/virt.c | 19 +++++++++++------ include/hw/intc/loongarch_pch_msi.h | 3 ++- include/hw/intc/loongarch_pch_pic.h | 5 ++--- include/hw/pci-host/ls7a.h | 1 - 6 files changed, 71 insertions(+), 19 deletions(-)